haswell: RESET_ON_INVALID_RAMSTAGE_CACHE option
The RESET_ON_INVALID_RAMSTAGE_CACHE option indicates what to do
when the ramstage cache is found to be invalid on a S3 wake. If
selected the system will perform a system reset on S3 wake when the
ramstage cache is invalid. Otherwise it will signal to load the
ramstage from cbfs.
Change-Id: I8f21fcfc7f95fb3377ed2932868aa49a68904803
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2807
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index d491c7e..4ece6c2 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -36,6 +36,7 @@
#include <cbmem.h>
#include <cbfs.h>
#include <romstage_handoff.h>
+#include <reset.h>
#if CONFIG_CHROMEOS
#include <vendorcode/google/chromeos/chromeos.h>
#endif
@@ -46,6 +47,14 @@
#include "southbridge/intel/lynxpoint/me.h"
+static inline void reset_system(void)
+{
+ hard_reset();
+ while (1) {
+ hlt();
+ }
+}
+
/* The cache-as-ram assembly file calls romstage_main() after setting up
* cache-as-ram. romstage_main() will then call the mainboards's
* mainboard_romstage_entry() function. That function then calls
@@ -271,10 +280,7 @@
#if CONFIG_HAVE_ACPI_RESUME
if (wake_from_s3 && !cbmem_was_initted) {
/* Failed S3 resume, reset to come up cleanly */
- outb(0x6, 0xcf9);
- while (1) {
- hlt();
- }
+ reset_system();
}
#endif
@@ -375,6 +381,9 @@
if (cache->magic != RAMSTAGE_CACHE_MAGIC) {
printk(BIOS_DEBUG, "Invalid ramstage cache found.\n");
+ #if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE
+ reset_system();
+ #endif
return NULL;
}