Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 ChromeOS Authors |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <stdint.h> |
Aaron Durbin | 7492ec1 | 2013-02-08 22:18:04 -0600 | [diff] [blame] | 21 | #include <string.h> |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 22 | #include <cbmem.h> |
| 23 | #include <console/console.h> |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 24 | #include <arch/cpu.h> |
| 25 | #include <cpu/x86/bist.h> |
| 26 | #include <cpu/x86/msr.h> |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 27 | #include <cpu/x86/mtrr.h> |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 28 | #include <halt.h> |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 29 | #include <lib.h> |
| 30 | #include <timestamp.h> |
| 31 | #include <arch/io.h> |
Aaron Durbin | 7492ec1 | 2013-02-08 22:18:04 -0600 | [diff] [blame] | 32 | #include <arch/stages.h> |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 33 | #include <device/pci_def.h> |
| 34 | #include <cpu/x86/lapic.h> |
Aaron Durbin | f7cdfe5 | 2013-02-16 00:05:52 -0600 | [diff] [blame] | 35 | #include <cbfs.h> |
Aaron Durbin | 75e2974 | 2013-10-10 20:37:04 -0500 | [diff] [blame] | 36 | #include <ramstage_cache.h> |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 37 | #include <romstage_handoff.h> |
Aaron Durbin | b86113f | 2013-02-19 08:59:16 -0600 | [diff] [blame] | 38 | #include <reset.h> |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 39 | #include <vendorcode/google/chromeos/chromeos.h> |
Duncan Laurie | 7cced0d | 2013-06-04 10:03:34 -0700 | [diff] [blame] | 40 | #if CONFIG_EC_GOOGLE_CHROMEEC |
| 41 | #include <ec/google/chromeec/ec.h> |
| 42 | #endif |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 43 | #include "haswell.h" |
| 44 | #include "northbridge/intel/haswell/haswell.h" |
| 45 | #include "northbridge/intel/haswell/raminit.h" |
| 46 | #include "southbridge/intel/lynxpoint/pch.h" |
| 47 | #include "southbridge/intel/lynxpoint/me.h" |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 48 | |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 49 | |
Aaron Durbin | b86113f | 2013-02-19 08:59:16 -0600 | [diff] [blame] | 50 | static inline void reset_system(void) |
| 51 | { |
| 52 | hard_reset(); |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 53 | halt(); |
Aaron Durbin | b86113f | 2013-02-19 08:59:16 -0600 | [diff] [blame] | 54 | } |
| 55 | |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 56 | /* The cache-as-ram assembly file calls romstage_main() after setting up |
| 57 | * cache-as-ram. romstage_main() will then call the mainboards's |
| 58 | * mainboard_romstage_entry() function. That function then calls |
| 59 | * romstage_common() below. The reason for the back and forth is to provide |
| 60 | * common entry point from cache-as-ram while still allowing for code sharing. |
| 61 | * Because we can't use global variables the stack is used for allocations -- |
| 62 | * thus the need to call back and forth. */ |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 63 | |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 64 | |
| 65 | static inline u32 *stack_push(u32 *stack, u32 value) |
| 66 | { |
| 67 | stack = &stack[-1]; |
| 68 | *stack = value; |
| 69 | return stack; |
| 70 | } |
| 71 | |
Aaron Durbin | c0cbd6e | 2013-03-13 13:51:20 -0500 | [diff] [blame] | 72 | /* Romstage needs quite a bit of stack for decompressing images since the lzma |
| 73 | * lib keeps its state on the stack during romstage. */ |
| 74 | #define ROMSTAGE_RAM_STACK_SIZE 0x5000 |
Aaron Durbin | e2d9e5b | 2013-02-08 17:38:35 -0600 | [diff] [blame] | 75 | static unsigned long choose_top_of_stack(void) |
| 76 | { |
| 77 | unsigned long stack_top; |
Kyösti Mälkki | ae98e83 | 2014-11-28 11:24:19 +0200 | [diff] [blame] | 78 | |
Aaron Durbin | c0cbd6e | 2013-03-13 13:51:20 -0500 | [diff] [blame] | 79 | /* cbmem_add() does a find() before add(). */ |
| 80 | stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, |
| 81 | ROMSTAGE_RAM_STACK_SIZE); |
| 82 | stack_top += ROMSTAGE_RAM_STACK_SIZE; |
Aaron Durbin | e2d9e5b | 2013-02-08 17:38:35 -0600 | [diff] [blame] | 83 | return stack_top; |
| 84 | } |
| 85 | |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 86 | /* setup_romstage_stack_after_car() determines the stack to use after |
| 87 | * cache-as-ram is torn down as well as the MTRR settings to use. */ |
| 88 | static void *setup_romstage_stack_after_car(void) |
| 89 | { |
| 90 | unsigned long top_of_stack; |
| 91 | int num_mtrrs; |
| 92 | u32 *slot; |
| 93 | u32 mtrr_mask_upper; |
Aaron Durbin | 67481ddc | 2013-02-15 15:08:37 -0600 | [diff] [blame] | 94 | u32 top_of_ram; |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 95 | |
| 96 | /* Top of stack needs to be aligned to a 4-byte boundary. */ |
Aaron Durbin | e2d9e5b | 2013-02-08 17:38:35 -0600 | [diff] [blame] | 97 | top_of_stack = choose_top_of_stack() & ~3; |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 98 | slot = (void *)top_of_stack; |
| 99 | num_mtrrs = 0; |
| 100 | |
| 101 | /* The upper bits of the MTRR mask need to set according to the number |
| 102 | * of physical address bits. */ |
| 103 | mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1; |
| 104 | |
Paul Menzel | 4fe9813 | 2014-01-25 15:55:28 +0100 | [diff] [blame] | 105 | /* The order for each MTRR is value then base with upper 32-bits of |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 106 | * each value coming before the lower 32-bits. The reasoning for |
| 107 | * this ordering is to create a stack layout like the following: |
| 108 | * +0: Number of MTRRs |
Paul Menzel | 4fe9813 | 2014-01-25 15:55:28 +0100 | [diff] [blame] | 109 | * +4: MTRR base 0 31:0 |
| 110 | * +8: MTRR base 0 63:32 |
| 111 | * +12: MTRR mask 0 31:0 |
| 112 | * +16: MTRR mask 0 63:32 |
| 113 | * +20: MTRR base 1 31:0 |
| 114 | * +24: MTRR base 1 63:32 |
| 115 | * +28: MTRR mask 1 31:0 |
| 116 | * +32: MTRR mask 1 63:32 |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 117 | */ |
| 118 | |
| 119 | /* Cache the ROM as WP just below 4GiB. */ |
| 120 | slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ |
Kyösti Mälkki | 107f72e | 2014-01-06 11:06:26 +0200 | [diff] [blame] | 121 | slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid); |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 122 | slot = stack_push(slot, 0); /* upper base */ |
Kyösti Mälkki | 107f72e | 2014-01-06 11:06:26 +0200 | [diff] [blame] | 123 | slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 124 | num_mtrrs++; |
| 125 | |
| 126 | /* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */ |
| 127 | slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ |
| 128 | slot = stack_push(slot, ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid); |
| 129 | slot = stack_push(slot, 0); /* upper base */ |
| 130 | slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK); |
| 131 | num_mtrrs++; |
| 132 | |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 133 | top_of_ram = (uint32_t)cbmem_top(); |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 134 | /* Cache 8MiB below the top of ram. On haswell systems the top of |
| 135 | * ram under 4GiB is the start of the TSEG region. It is required to |
| 136 | * be 8MiB aligned. Set this area as cacheable so it can be used later |
| 137 | * for ramstage before setting up the entire RAM as cacheable. */ |
| 138 | slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ |
| 139 | slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid); |
| 140 | slot = stack_push(slot, 0); /* upper base */ |
Aaron Durbin | 67481ddc | 2013-02-15 15:08:37 -0600 | [diff] [blame] | 141 | slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK); |
| 142 | num_mtrrs++; |
| 143 | |
| 144 | /* Cache 8MiB at the top of ram. Top of ram on haswell systems |
| 145 | * is where the TSEG region resides. However, it is not restricted |
| 146 | * to SMM mode until SMM has been relocated. By setting the region |
| 147 | * to cacheable it provides faster access when relocating the SMM |
| 148 | * handler as well as using the TSEG region for other purposes. */ |
| 149 | slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ |
| 150 | slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid); |
| 151 | slot = stack_push(slot, 0); /* upper base */ |
| 152 | slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK); |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 153 | num_mtrrs++; |
| 154 | |
Paul Menzel | 4fe9813 | 2014-01-25 15:55:28 +0100 | [diff] [blame] | 155 | /* Save the number of MTRRs to setup. Return the stack location |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 156 | * pointing to the number of MTRRs. */ |
| 157 | slot = stack_push(slot, num_mtrrs); |
| 158 | |
| 159 | return slot; |
| 160 | } |
| 161 | |
Aaron Durbin | 39ecc65 | 2013-05-02 09:42:13 -0500 | [diff] [blame] | 162 | void * asmlinkage romstage_main(unsigned long bist) |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 163 | { |
| 164 | int i; |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 165 | void *romstage_stack_after_car; |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 166 | const int num_guards = 4; |
| 167 | const u32 stack_guard = 0xdeadbeef; |
| 168 | u32 *stack_base = (void *)(CONFIG_DCACHE_RAM_BASE + |
| 169 | CONFIG_DCACHE_RAM_SIZE - |
| 170 | CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE); |
| 171 | |
| 172 | printk(BIOS_DEBUG, "Setting up stack guards.\n"); |
| 173 | for (i = 0; i < num_guards; i++) |
| 174 | stack_base[i] = stack_guard; |
| 175 | |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 176 | mainboard_romstage_entry(bist); |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 177 | |
| 178 | /* Check the stack. */ |
| 179 | for (i = 0; i < num_guards; i++) { |
| 180 | if (stack_base[i] == stack_guard) |
| 181 | continue; |
| 182 | printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n"); |
| 183 | } |
| 184 | |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 185 | /* Get the stack to use after cache-as-ram is torn down. */ |
| 186 | romstage_stack_after_car = setup_romstage_stack_after_car(); |
| 187 | |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 188 | return romstage_stack_after_car; |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 189 | } |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 190 | |
| 191 | void romstage_common(const struct romstage_params *params) |
| 192 | { |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 193 | int boot_mode; |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 194 | int wake_from_s3; |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 195 | struct romstage_handoff *handoff; |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 196 | |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 197 | timestamp_init(get_initial_timestamp()); |
| 198 | timestamp_add_now(TS_START_ROMSTAGE); |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 199 | |
| 200 | if (params->bist == 0) |
| 201 | enable_lapic(); |
| 202 | |
| 203 | wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config); |
| 204 | |
Duncan Laurie | 7cced0d | 2013-06-04 10:03:34 -0700 | [diff] [blame] | 205 | #if CONFIG_EC_GOOGLE_CHROMEEC |
| 206 | /* Ensure the EC is in the right mode for recovery */ |
| 207 | google_chromeec_early_init(); |
| 208 | #endif |
| 209 | |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 210 | /* Halt if there was a built in self test failure */ |
| 211 | report_bist_failure(params->bist); |
| 212 | |
| 213 | /* Perform some early chipset initialization required |
| 214 | * before RAM initialization can work |
| 215 | */ |
| 216 | haswell_early_initialization(HASWELL_MOBILE); |
| 217 | printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n"); |
| 218 | |
| 219 | if (wake_from_s3) { |
| 220 | #if CONFIG_HAVE_ACPI_RESUME |
| 221 | printk(BIOS_DEBUG, "Resume from S3 detected.\n"); |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 222 | #else |
| 223 | printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 224 | wake_from_s3 = 0; |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 225 | #endif |
| 226 | } |
| 227 | |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 228 | /* There are hard coded assumptions of 2 meaning s3 wake. Normalize |
| 229 | * the users of the 2 literal here based off wake_from_s3. */ |
| 230 | boot_mode = wake_from_s3 ? 2 : 0; |
| 231 | |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 232 | /* Prepare USB controller early in S3 resume */ |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 233 | if (wake_from_s3) |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 234 | enable_usb_bar(); |
| 235 | |
| 236 | post_code(0x3a); |
| 237 | params->pei_data->boot_mode = boot_mode; |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 238 | |
| 239 | timestamp_add_now(TS_BEFORE_INITRAM); |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 240 | |
| 241 | report_platform_info(); |
| 242 | |
Aaron Durbin | c7633f4 | 2013-06-13 17:29:36 -0700 | [diff] [blame] | 243 | if (params->copy_spd != NULL) |
| 244 | params->copy_spd(params->pei_data); |
| 245 | |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 246 | sdram_initialize(params->pei_data); |
| 247 | |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 248 | timestamp_add_now(TS_AFTER_INITRAM); |
| 249 | |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 250 | post_code(0x3b); |
| 251 | |
| 252 | intel_early_me_status(); |
| 253 | |
| 254 | quick_ram_check(); |
| 255 | post_code(0x3e); |
| 256 | |
Aaron Durbin | c0cbd6e | 2013-03-13 13:51:20 -0500 | [diff] [blame] | 257 | if (!wake_from_s3) { |
| 258 | cbmem_initialize_empty(); |
| 259 | /* Save data returned from MRC on non-S3 resumes. */ |
Aaron Durbin | 2ad1dba | 2013-02-07 00:51:18 -0600 | [diff] [blame] | 260 | save_mrc_data(params->pei_data); |
Aaron Durbin | c0cbd6e | 2013-03-13 13:51:20 -0500 | [diff] [blame] | 261 | } else if (cbmem_initialize()) { |
| 262 | #if CONFIG_HAVE_ACPI_RESUME |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 263 | /* Failed S3 resume, reset to come up cleanly */ |
Aaron Durbin | b86113f | 2013-02-19 08:59:16 -0600 | [diff] [blame] | 264 | reset_system(); |
Aaron Durbin | c0cbd6e | 2013-03-13 13:51:20 -0500 | [diff] [blame] | 265 | #endif |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 266 | } |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 267 | |
| 268 | handoff = romstage_handoff_find_or_add(); |
| 269 | if (handoff != NULL) |
| 270 | handoff->s3_resume = wake_from_s3; |
| 271 | else |
| 272 | printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); |
| 273 | |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 274 | post_code(0x3f); |
| 275 | #if CONFIG_CHROMEOS |
| 276 | init_chromeos(boot_mode); |
| 277 | #endif |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 278 | timestamp_add_now(TS_END_ROMSTAGE); |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 279 | } |
Aaron Durbin | 7492ec1 | 2013-02-08 22:18:04 -0600 | [diff] [blame] | 280 | |
Aaron Durbin | d02bb62 | 2013-03-01 17:40:49 -0600 | [diff] [blame] | 281 | static inline void prepare_for_resume(struct romstage_handoff *handoff) |
Aaron Durbin | 7492ec1 | 2013-02-08 22:18:04 -0600 | [diff] [blame] | 282 | { |
Aaron Durbin | e2d9e5b | 2013-02-08 17:38:35 -0600 | [diff] [blame] | 283 | /* Only need to save memory when ramstage isn't relocatable. */ |
| 284 | #if !CONFIG_RELOCATABLE_RAMSTAGE |
Aaron Durbin | 7492ec1 | 2013-02-08 22:18:04 -0600 | [diff] [blame] | 285 | #if CONFIG_HAVE_ACPI_RESUME |
| 286 | /* Back up the OS-controlled memory where ramstage will be loaded. */ |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 287 | if (handoff != NULL && handoff->s3_resume) { |
Aaron Durbin | 7492ec1 | 2013-02-08 22:18:04 -0600 | [diff] [blame] | 288 | void *src = (void *)CONFIG_RAMBASE; |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 289 | void *dest = cbmem_find(CBMEM_ID_RESUME); |
| 290 | if (dest != NULL) |
| 291 | memcpy(dest, src, HIGH_MEMORY_SAVE); |
Aaron Durbin | 7492ec1 | 2013-02-08 22:18:04 -0600 | [diff] [blame] | 292 | } |
| 293 | #endif |
Aaron Durbin | e2d9e5b | 2013-02-08 17:38:35 -0600 | [diff] [blame] | 294 | #endif |
Aaron Durbin | 7492ec1 | 2013-02-08 22:18:04 -0600 | [diff] [blame] | 295 | } |
| 296 | |
| 297 | void romstage_after_car(void) |
| 298 | { |
Aaron Durbin | d02bb62 | 2013-03-01 17:40:49 -0600 | [diff] [blame] | 299 | struct romstage_handoff *handoff; |
| 300 | |
| 301 | handoff = romstage_handoff_find_or_add(); |
| 302 | |
| 303 | prepare_for_resume(handoff); |
| 304 | |
Aaron Durbin | 7492ec1 | 2013-02-08 22:18:04 -0600 | [diff] [blame] | 305 | /* Load the ramstage. */ |
Stefan Reinauer | 648d166 | 2013-05-06 18:05:39 -0700 | [diff] [blame] | 306 | copy_and_run(); |
Aaron Durbin | 7492ec1 | 2013-02-08 22:18:04 -0600 | [diff] [blame] | 307 | } |
Aaron Durbin | f7cdfe5 | 2013-02-16 00:05:52 -0600 | [diff] [blame] | 308 | |
| 309 | |
| 310 | #if CONFIG_RELOCATABLE_RAMSTAGE |
Aaron Durbin | 75e2974 | 2013-10-10 20:37:04 -0500 | [diff] [blame] | 311 | #include <ramstage_cache.h> |
| 312 | |
| 313 | struct ramstage_cache *ramstage_cache_location(long *size) |
Aaron Durbin | f7cdfe5 | 2013-02-16 00:05:52 -0600 | [diff] [blame] | 314 | { |
Aaron Durbin | f7cdfe5 | 2013-02-16 00:05:52 -0600 | [diff] [blame] | 315 | /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. |
| 316 | * The top of ram is defined to be the TSEG base address. */ |
Aaron Durbin | 75e2974 | 2013-10-10 20:37:04 -0500 | [diff] [blame] | 317 | *size = RESERVED_SMM_SIZE; |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 318 | return (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); |
Aaron Durbin | f7cdfe5 | 2013-02-16 00:05:52 -0600 | [diff] [blame] | 319 | } |
| 320 | |
Aaron Durbin | 75e2974 | 2013-10-10 20:37:04 -0500 | [diff] [blame] | 321 | void ramstage_cache_invalid(struct ramstage_cache *cache) |
Aaron Durbin | f7cdfe5 | 2013-02-16 00:05:52 -0600 | [diff] [blame] | 322 | { |
Aaron Durbin | 75e2974 | 2013-10-10 20:37:04 -0500 | [diff] [blame] | 323 | #if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE |
| 324 | reset_system(); |
| 325 | #endif |
Aaron Durbin | f7cdfe5 | 2013-02-16 00:05:52 -0600 | [diff] [blame] | 326 | } |
| 327 | #endif |