Angel Pons | f23ae0b | 2020-04-02 23:48:12 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 2 | |
Martin Roth | c87ab01 | 2022-11-20 19:32:51 -0700 | [diff] [blame] | 3 | #include <cpu/intel/post_codes.h> |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 4 | #include <cpu/x86/mtrr.h> |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 5 | #include <cpu/x86/cache.h> |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 6 | #include <cpu/x86/post_code.h> |
| 7 | |
Kyösti Mälkki | 7522a8f | 2020-11-20 16:47:38 +0200 | [diff] [blame] | 8 | .section .init |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 9 | .global bootblock_pre_c_entry |
| 10 | |
Kyösti Mälkki | aea8eec | 2018-06-04 08:49:17 +0300 | [diff] [blame] | 11 | .code32 |
| 12 | _cache_as_ram_setup: |
| 13 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 14 | bootblock_pre_c_entry: |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 15 | |
| 16 | cache_as_ram: |
Martin Roth | c87ab01 | 2022-11-20 19:32:51 -0700 | [diff] [blame] | 17 | post_code(POST_BOOTBLOCK_CAR) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 18 | |
Kyösti Mälkki | 5bc46d8 | 2018-06-14 06:21:53 +0300 | [diff] [blame] | 19 | /* Clear/disable fixed MTRRs */ |
| 20 | mov $fixed_mtrr_list_size, %ebx |
| 21 | xor %eax, %eax |
| 22 | xor %edx, %edx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 23 | |
Kyösti Mälkki | 5bc46d8 | 2018-06-14 06:21:53 +0300 | [diff] [blame] | 24 | clear_fixed_mtrr: |
| 25 | add $-2, %ebx |
| 26 | movzwl fixed_mtrr_list(%ebx), %ecx |
| 27 | wrmsr |
| 28 | jnz clear_fixed_mtrr |
| 29 | |
Elyes HAOUAS | 02820ca | 2018-09-30 07:44:39 +0200 | [diff] [blame] | 30 | /* Figure out how many MTRRs we have, and clear them out */ |
Kyösti Mälkki | 5bc46d8 | 2018-06-14 06:21:53 +0300 | [diff] [blame] | 31 | mov $MTRR_CAP_MSR, %ecx |
| 32 | rdmsr |
| 33 | movzb %al, %ebx /* Number of variable MTRRs */ |
| 34 | mov $MTRR_PHYS_BASE(0), %ecx |
| 35 | xor %eax, %eax |
| 36 | xor %edx, %edx |
| 37 | |
| 38 | clear_var_mtrr: |
| 39 | wrmsr |
| 40 | inc %ecx |
| 41 | wrmsr |
| 42 | inc %ecx |
| 43 | dec %ebx |
| 44 | jnz clear_var_mtrr |
Martin Roth | c87ab01 | 2022-11-20 19:32:51 -0700 | [diff] [blame] | 45 | post_code(POST_SOC_SET_DEF_MTRR_TYPE) |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 46 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 47 | /* Configure the default memory type to uncacheable. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 48 | movl $MTRR_DEF_TYPE_MSR, %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 49 | rdmsr |
| 50 | andl $(~0x00000cff), %eax |
| 51 | wrmsr |
| 52 | |
Martin Roth | c87ab01 | 2022-11-20 19:32:51 -0700 | [diff] [blame] | 53 | post_code(POST_SOC_DETERMINE_CPU_ADDR_BITS) |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 54 | |
Kyösti Mälkki | 54d6a28 | 2018-05-25 06:03:14 +0300 | [diff] [blame] | 55 | /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 56 | movl $1, %eax |
| 57 | cpuid |
Elyes HAOUAS | 168ef39 | 2017-06-27 22:54:42 +0200 | [diff] [blame] | 58 | andl $(1 << 6 | 1 << 17), %edx /* PAE or PSE36 */ |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 59 | jz addrsize_set_high |
| 60 | movl $0x0f, %edx |
| 61 | |
| 62 | /* Preload high word of address mask (in %edx) for Variable |
Kyösti Mälkki | 54d6a28 | 2018-05-25 06:03:14 +0300 | [diff] [blame] | 63 | MTRRs 0 and 1. */ |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 64 | addrsize_set_high: |
| 65 | xorl %eax, %eax |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 66 | movl $MTRR_PHYS_MASK(0), %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 67 | wrmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 68 | movl $MTRR_PHYS_MASK(1), %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 69 | wrmsr |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 70 | |
Martin Roth | c87ab01 | 2022-11-20 19:32:51 -0700 | [diff] [blame] | 71 | post_code(POST_SOC_SET_CAR_BASE) |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 72 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 73 | /* Set Cache-as-RAM base address. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 74 | movl $(MTRR_PHYS_BASE(0)), %ecx |
Kyösti Mälkki | dc6bb6c | 2019-11-08 00:08:55 +0200 | [diff] [blame] | 75 | movl $_car_mtrr_start, %eax |
| 76 | orl $MTRR_TYPE_WRBACK, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 77 | xorl %edx, %edx |
| 78 | wrmsr |
| 79 | |
| 80 | /* Set Cache-as-RAM mask. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 81 | movl $(MTRR_PHYS_MASK(0)), %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 82 | rdmsr |
Kyösti Mälkki | dc6bb6c | 2019-11-08 00:08:55 +0200 | [diff] [blame] | 83 | movl $_car_mtrr_mask, %eax |
| 84 | orl $MTRR_PHYS_MASK_VALID, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 85 | wrmsr |
| 86 | |
Martin Roth | c87ab01 | 2022-11-20 19:32:51 -0700 | [diff] [blame] | 87 | post_code(POST_SOC_ENABLE_MTRRS) |
Kyösti Mälkki | 8a2f167 | 2016-07-20 13:29:59 +0300 | [diff] [blame] | 88 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 89 | /* Enable MTRR. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 90 | movl $MTRR_DEF_TYPE_MSR, %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 91 | rdmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 92 | orl $MTRR_DEF_TYPE_EN, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 93 | wrmsr |
| 94 | |
Martin Roth | c87ab01 | 2022-11-20 19:32:51 -0700 | [diff] [blame] | 95 | post_code(POST_SOC_ENABLE_CACHE) |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 96 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 97 | /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 98 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 99 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 100 | invd |
| 101 | movl %eax, %cr0 |
| 102 | |
Kyösti Mälkki | 54d6a28 | 2018-05-25 06:03:14 +0300 | [diff] [blame] | 103 | /* Read then clear the CAR region. This will also fill up the cache. |
| 104 | * IMPORTANT: The read is mandatory. |
| 105 | */ |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 106 | cld |
Kyösti Mälkki | dc6bb6c | 2019-11-08 00:08:55 +0200 | [diff] [blame] | 107 | movl $_car_mtrr_start, %edi |
| 108 | movl $_car_mtrr_size, %ecx |
| 109 | shr $2, %ecx |
| 110 | movl %ecx, %ebx |
| 111 | movl %edi, %esi |
Kyösti Mälkki | 54d6a28 | 2018-05-25 06:03:14 +0300 | [diff] [blame] | 112 | rep lodsl |
Kyösti Mälkki | dc6bb6c | 2019-11-08 00:08:55 +0200 | [diff] [blame] | 113 | movl %ebx, %ecx |
Kyösti Mälkki | 54d6a28 | 2018-05-25 06:03:14 +0300 | [diff] [blame] | 114 | xorl %eax, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 115 | rep stosl |
| 116 | |
Martin Roth | c87ab01 | 2022-11-20 19:32:51 -0700 | [diff] [blame] | 117 | post_code(POST_SOC_DISABLE_CACHE) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 118 | /* Enable Cache-as-RAM mode by disabling cache. */ |
| 119 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 120 | orl $CR0_CacheDisable, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 121 | movl %eax, %cr0 |
| 122 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 123 | /* Enable cache for our code in Flash because we do XIP here */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 124 | movl $MTRR_PHYS_BASE(1), %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 125 | xorl %edx, %edx |
Kyösti Mälkki | ce9f422 | 2018-06-25 18:53:36 +0300 | [diff] [blame] | 126 | movl $_program, %eax |
Kyösti Mälkki | dc6bb6c | 2019-11-08 00:08:55 +0200 | [diff] [blame] | 127 | andl $_xip_mtrr_mask, %eax |
Kyösti Mälkki | dc4820b | 2016-07-21 19:51:01 +0300 | [diff] [blame] | 128 | orl $MTRR_TYPE_WRPROT, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 129 | wrmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 130 | movl $MTRR_PHYS_MASK(1), %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 131 | rdmsr |
Kyösti Mälkki | dc6bb6c | 2019-11-08 00:08:55 +0200 | [diff] [blame] | 132 | movl $_xip_mtrr_mask, %eax |
| 133 | orl $MTRR_PHYS_MASK_VALID, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 134 | wrmsr |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 135 | |
Martin Roth | c87ab01 | 2022-11-20 19:32:51 -0700 | [diff] [blame] | 136 | post_code(POST_SOC_FILL_CACHE) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 137 | /* Enable cache. */ |
| 138 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 139 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 140 | movl %eax, %cr0 |
| 141 | |
Kyösti Mälkki | 39915bc | 2016-11-08 12:13:15 +0200 | [diff] [blame] | 142 | /* Setup the stack. */ |
Arthur Heymans | df9cdcf | 2019-11-09 06:50:20 +0100 | [diff] [blame] | 143 | mov $_ecar_stack, %esp |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 144 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 145 | /* Need to align stack to 16 bytes at call instruction. Account for |
| 146 | the pushes below. */ |
| 147 | andl $0xfffffff0, %esp |
| 148 | subl $4, %esp |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 149 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 150 | /* push TSC and BIST to stack */ |
| 151 | movd %mm0, %eax |
Elyes HAOUAS | 87930b3 | 2019-01-16 12:41:57 +0100 | [diff] [blame] | 152 | pushl %eax /* BIST */ |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 153 | movd %mm2, %eax |
| 154 | pushl %eax /* tsc[63:32] */ |
| 155 | movd %mm1, %eax |
Elyes HAOUAS | 87930b3 | 2019-01-16 12:41:57 +0100 | [diff] [blame] | 156 | pushl %eax /* tsc[31:0] */ |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 157 | |
| 158 | before_c_entry: |
Martin Roth | c87ab01 | 2022-11-20 19:32:51 -0700 | [diff] [blame] | 159 | post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY) |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 160 | call bootblock_c_entry_bist |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 161 | |
Kyösti Mälkki | aea8eec | 2018-06-04 08:49:17 +0300 | [diff] [blame] | 162 | /* Should never see this postcode */ |
| 163 | post_code(POST_DEAD_CODE) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 164 | |
| 165 | .Lhlt: |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 166 | hlt |
| 167 | jmp .Lhlt |
| 168 | |
Kyösti Mälkki | 5bc46d8 | 2018-06-14 06:21:53 +0300 | [diff] [blame] | 169 | fixed_mtrr_list: |
| 170 | .word MTRR_FIX_64K_00000 |
| 171 | .word MTRR_FIX_16K_80000 |
| 172 | .word MTRR_FIX_16K_A0000 |
| 173 | .word MTRR_FIX_4K_C0000 |
| 174 | .word MTRR_FIX_4K_C8000 |
| 175 | .word MTRR_FIX_4K_D0000 |
| 176 | .word MTRR_FIX_4K_D8000 |
| 177 | .word MTRR_FIX_4K_E0000 |
| 178 | .word MTRR_FIX_4K_E8000 |
| 179 | .word MTRR_FIX_4K_F0000 |
| 180 | .word MTRR_FIX_4K_F8000 |
| 181 | fixed_mtrr_list_size = . - fixed_mtrr_list |
Kyösti Mälkki | aea8eec | 2018-06-04 08:49:17 +0300 | [diff] [blame] | 182 | |
| 183 | _cache_as_ram_setup_end: |