Angel Pons | ba38f37 | 2020-04-05 15:46:45 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
| 5 | #include <device/pci.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Aaron Durbin | 789f2b6 | 2015-09-09 17:05:06 -0500 | [diff] [blame] | 7 | #include <fsp/util.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 8 | #include <soc/pci_devs.h> |
| 9 | #include <soc/ramstage.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 10 | |
Elyes HAOUAS | c338507 | 2019-03-21 15:38:06 +0100 | [diff] [blame] | 11 | #include "chip.h" |
| 12 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 13 | static struct device_operations pci_domain_ops = { |
| 14 | .read_resources = pci_domain_read_resources, |
| 15 | .set_resources = pci_domain_set_resources, |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 16 | .scan_bus = pci_domain_scan_bus, |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 17 | }; |
| 18 | |
| 19 | static struct device_operations cpu_bus_ops = { |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame] | 20 | .read_resources = noop_read_resources, |
| 21 | .set_resources = noop_set_resources, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 22 | .init = soc_init_cpus |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 23 | }; |
| 24 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 25 | static void enable_dev(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 26 | { |
| 27 | /* Set the operations if it is a special bus type */ |
| 28 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 29 | dev->ops = &pci_domain_ops; |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 30 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 31 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 32 | dev->ops = &cpu_bus_ops; |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 33 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 34 | } else if (dev->path.type == DEVICE_PATH_PCI) { |
| 35 | /* Handle south cluster enablement. */ |
| 36 | if (PCI_SLOT(dev->path.pci.devfn) > GFX_DEV && |
| 37 | (dev->ops == NULL || dev->ops->enable == NULL)) { |
| 38 | southcluster_enable_dev(dev); |
| 39 | } |
| 40 | } |
| 41 | } |
| 42 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 43 | __weak void board_silicon_USB2_override(SILICON_INIT_UPD *params) |
Matt DeVillier | 2c8ac22 | 2017-08-26 04:53:35 -0500 | [diff] [blame] | 44 | { |
| 45 | } |
| 46 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 47 | void soc_silicon_init_params(SILICON_INIT_UPD *params) |
| 48 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 49 | struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC); |
Ravi Sarawadi | d077b58 | 2015-09-09 14:12:16 -0700 | [diff] [blame] | 50 | struct soc_intel_braswell_config *config; |
| 51 | |
| 52 | if (!dev) { |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 53 | printk(BIOS_ERR, "Error! Device (%s) not found, soc_silicon_init_params!\n", |
| 54 | dev_path(dev)); |
Ravi Sarawadi | d077b58 | 2015-09-09 14:12:16 -0700 | [diff] [blame] | 55 | return; |
| 56 | } |
| 57 | |
Kyösti Mälkki | 8950cfb | 2019-07-13 22:16:25 +0300 | [diff] [blame] | 58 | config = config_of(dev); |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 59 | |
| 60 | /* Set the parameters for SiliconInit */ |
| 61 | printk(BIOS_DEBUG, "Updating UPD values for SiliconInit\n"); |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 62 | params->PcdSdcardMode = config->PcdSdcardMode; |
| 63 | params->PcdEnableHsuart0 = config->PcdEnableHsuart0; |
| 64 | params->PcdEnableHsuart1 = config->PcdEnableHsuart1; |
| 65 | params->PcdEnableAzalia = config->PcdEnableAzalia; |
| 66 | params->PcdEnableSata = config->PcdEnableSata; |
| 67 | params->PcdEnableXhci = config->PcdEnableXhci; |
| 68 | params->PcdEnableLpe = config->PcdEnableLpe; |
| 69 | params->PcdEnableDma0 = config->PcdEnableDma0; |
| 70 | params->PcdEnableDma1 = config->PcdEnableDma1; |
| 71 | params->PcdEnableI2C0 = config->PcdEnableI2C0; |
| 72 | params->PcdEnableI2C1 = config->PcdEnableI2C1; |
| 73 | params->PcdEnableI2C2 = config->PcdEnableI2C2; |
| 74 | params->PcdEnableI2C3 = config->PcdEnableI2C3; |
| 75 | params->PcdEnableI2C4 = config->PcdEnableI2C4; |
| 76 | params->PcdEnableI2C5 = config->PcdEnableI2C5; |
| 77 | params->PcdEnableI2C6 = config->PcdEnableI2C6; |
| 78 | params->GraphicsConfigPtr = 0; |
| 79 | params->AzaliaConfigPtr = 0; |
| 80 | params->PunitPwrConfigDisable = config->PunitPwrConfigDisable; |
| 81 | params->ChvSvidConfig = config->ChvSvidConfig; |
| 82 | params->DptfDisable = config->DptfDisable; |
| 83 | params->PcdEmmcMode = config->PcdEmmcMode; |
| 84 | params->PcdUsb3ClkSsc = config->PcdUsb3ClkSsc; |
| 85 | params->PcdDispClkSsc = config->PcdDispClkSsc; |
| 86 | params->PcdSataClkSsc = config->PcdSataClkSsc; |
Kevin Chiu | 348a6d5 | 2016-06-30 14:50:52 +0800 | [diff] [blame] | 87 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 88 | params->Usb2Port0PerPortPeTxiSet = config->Usb2Port0PerPortPeTxiSet; |
| 89 | params->Usb2Port0PerPortTxiSet = config->Usb2Port0PerPortTxiSet; |
| 90 | params->Usb2Port0IUsbTxEmphasisEn = config->Usb2Port0IUsbTxEmphasisEn; |
| 91 | params->Usb2Port0PerPortTxPeHalf = config->Usb2Port0PerPortTxPeHalf; |
Kevin Chiu | 348a6d5 | 2016-06-30 14:50:52 +0800 | [diff] [blame] | 92 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 93 | params->Usb2Port1PerPortPeTxiSet = config->Usb2Port1PerPortPeTxiSet; |
| 94 | params->Usb2Port1PerPortTxiSet = config->Usb2Port1PerPortTxiSet; |
| 95 | params->Usb2Port1IUsbTxEmphasisEn = config->Usb2Port1IUsbTxEmphasisEn; |
| 96 | params->Usb2Port1PerPortTxPeHalf = config->Usb2Port1PerPortTxPeHalf; |
Kevin Chiu | 348a6d5 | 2016-06-30 14:50:52 +0800 | [diff] [blame] | 97 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 98 | params->Usb2Port2PerPortPeTxiSet = config->Usb2Port2PerPortPeTxiSet; |
| 99 | params->Usb2Port2PerPortTxiSet = config->Usb2Port2PerPortTxiSet; |
| 100 | params->Usb2Port2IUsbTxEmphasisEn = config->Usb2Port2IUsbTxEmphasisEn; |
| 101 | params->Usb2Port2PerPortTxPeHalf = config->Usb2Port2PerPortTxPeHalf; |
Kevin Chiu | 348a6d5 | 2016-06-30 14:50:52 +0800 | [diff] [blame] | 102 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 103 | params->Usb2Port3PerPortPeTxiSet = config->Usb2Port3PerPortPeTxiSet; |
| 104 | params->Usb2Port3PerPortTxiSet = config->Usb2Port3PerPortTxiSet; |
| 105 | params->Usb2Port3IUsbTxEmphasisEn = config->Usb2Port3IUsbTxEmphasisEn; |
| 106 | params->Usb2Port3PerPortTxPeHalf = config->Usb2Port3PerPortTxPeHalf; |
Kevin Chiu | 348a6d5 | 2016-06-30 14:50:52 +0800 | [diff] [blame] | 107 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 108 | params->Usb2Port4PerPortPeTxiSet = config->Usb2Port4PerPortPeTxiSet; |
| 109 | params->Usb2Port4PerPortTxiSet = config->Usb2Port4PerPortTxiSet; |
| 110 | params->Usb2Port4IUsbTxEmphasisEn = config->Usb2Port4IUsbTxEmphasisEn; |
| 111 | params->Usb2Port4PerPortTxPeHalf = config->Usb2Port4PerPortTxPeHalf; |
| 112 | |
| 113 | params->Usb3Lane0Ow2tapgen2deemph3p5 = config->Usb3Lane0Ow2tapgen2deemph3p5; |
| 114 | params->Usb3Lane1Ow2tapgen2deemph3p5 = config->Usb3Lane1Ow2tapgen2deemph3p5; |
| 115 | params->Usb3Lane2Ow2tapgen2deemph3p5 = config->Usb3Lane2Ow2tapgen2deemph3p5; |
| 116 | params->Usb3Lane3Ow2tapgen2deemph3p5 = config->Usb3Lane3Ow2tapgen2deemph3p5; |
| 117 | |
| 118 | params->PcdSataInterfaceSpeed = config->PcdSataInterfaceSpeed; |
| 119 | params->PcdPchUsbSsicPort = config->PcdPchUsbSsicPort; |
| 120 | params->PcdPchUsbHsicPort = config->PcdPchUsbHsicPort; |
| 121 | params->PcdPcieRootPortSpeed = config->PcdPcieRootPortSpeed; |
| 122 | params->PcdPchSsicEnable = config->PcdPchSsicEnable; |
| 123 | params->PcdLogoPtr = config->PcdLogoPtr; |
| 124 | params->PcdLogoSize = config->PcdLogoSize; |
| 125 | params->PcdRtcLock = config->PcdRtcLock; |
| 126 | params->PMIC_I2CBus = config->PMIC_I2CBus; |
| 127 | params->ISPEnable = config->ISPEnable; |
| 128 | params->ISPPciDevConfig = config->ISPPciDevConfig; |
| 129 | params->PcdSdDetectChk = config->PcdSdDetectChk; |
| 130 | params->I2C0Frequency = config->I2C0Frequency; |
| 131 | params->I2C1Frequency = config->I2C1Frequency; |
| 132 | params->I2C2Frequency = config->I2C2Frequency; |
| 133 | params->I2C3Frequency = config->I2C3Frequency; |
| 134 | params->I2C4Frequency = config->I2C4Frequency; |
| 135 | params->I2C5Frequency = config->I2C5Frequency; |
| 136 | params->I2C6Frequency = config->I2C6Frequency; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 137 | |
Matt DeVillier | 2c8ac22 | 2017-08-26 04:53:35 -0500 | [diff] [blame] | 138 | board_silicon_USB2_override(params); |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 139 | } |
| 140 | |
Wim Vervoorn | 67117c3 | 2019-12-16 14:21:09 +0100 | [diff] [blame] | 141 | const struct cbmem_entry *soc_load_logo(SILICON_INIT_UPD *params) |
| 142 | { |
| 143 | return fsp_load_logo(¶ms->PcdLogoPtr, ¶ms->PcdLogoSize); |
| 144 | } |
| 145 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 146 | void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, SILICON_INIT_UPD *new) |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 147 | { |
| 148 | /* Display the parameters for SiliconInit */ |
| 149 | printk(BIOS_SPEW, "UPD values for SiliconInit:\n"); |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 150 | |
| 151 | fsp_display_upd_value("PcdSdcardMode", 1, |
| 152 | old->PcdSdcardMode, |
| 153 | new->PcdSdcardMode); |
| 154 | fsp_display_upd_value("PcdEnableHsuart0", 1, |
| 155 | old->PcdEnableHsuart0, |
| 156 | new->PcdEnableHsuart0); |
| 157 | fsp_display_upd_value("PcdEnableHsuart1", 1, |
| 158 | old->PcdEnableHsuart1, |
| 159 | new->PcdEnableHsuart1); |
| 160 | fsp_display_upd_value("PcdEnableAzalia", 1, |
| 161 | old->PcdEnableAzalia, |
| 162 | new->PcdEnableAzalia); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 163 | fsp_display_upd_value("AzaliaConfigPtr", 4, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 164 | (uint32_t)old->AzaliaConfigPtr, |
| 165 | (uint32_t)new->AzaliaConfigPtr); |
| 166 | |
| 167 | fsp_display_upd_value("PcdEnableSata", 1, old->PcdEnableSata, new->PcdEnableSata); |
| 168 | fsp_display_upd_value("PcdEnableXhci", 1, old->PcdEnableXhci, new->PcdEnableXhci); |
| 169 | fsp_display_upd_value("PcdEnableLpe", 1, old->PcdEnableLpe, new->PcdEnableLpe); |
| 170 | fsp_display_upd_value("PcdEnableDma0", 1, old->PcdEnableDma0, new->PcdEnableDma0); |
| 171 | fsp_display_upd_value("PcdEnableDma1", 1, old->PcdEnableDma1, new->PcdEnableDma1); |
| 172 | fsp_display_upd_value("PcdEnableI2C0", 1, old->PcdEnableI2C0, new->PcdEnableI2C0); |
| 173 | fsp_display_upd_value("PcdEnableI2C1", 1, old->PcdEnableI2C1, new->PcdEnableI2C1); |
| 174 | fsp_display_upd_value("PcdEnableI2C2", 1, old->PcdEnableI2C2, new->PcdEnableI2C2); |
| 175 | fsp_display_upd_value("PcdEnableI2C3", 1, old->PcdEnableI2C3, new->PcdEnableI2C3); |
| 176 | fsp_display_upd_value("PcdEnableI2C4", 1, old->PcdEnableI2C4, new->PcdEnableI2C4); |
| 177 | fsp_display_upd_value("PcdEnableI2C5", 1, old->PcdEnableI2C5, new->PcdEnableI2C5); |
| 178 | fsp_display_upd_value("PcdEnableI2C6", 1, old->PcdEnableI2C6, new->PcdEnableI2C6); |
| 179 | |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 180 | fsp_display_upd_value("PcdGraphicsConfigPtr", 4, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 181 | old->GraphicsConfigPtr, |
| 182 | new->GraphicsConfigPtr); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 183 | fsp_display_upd_value("GpioFamilyInitTablePtr", 4, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 184 | (uint32_t)old->GpioFamilyInitTablePtr, |
| 185 | (uint32_t)new->GpioFamilyInitTablePtr); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 186 | fsp_display_upd_value("GpioPadInitTablePtr", 4, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 187 | (uint32_t)old->GpioPadInitTablePtr, |
| 188 | (uint32_t)new->GpioPadInitTablePtr); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 189 | fsp_display_upd_value("PunitPwrConfigDisable", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 190 | old->PunitPwrConfigDisable, |
| 191 | new->PunitPwrConfigDisable); |
| 192 | |
| 193 | fsp_display_upd_value("ChvSvidConfig", 1, old->ChvSvidConfig, new->ChvSvidConfig); |
| 194 | fsp_display_upd_value("DptfDisable", 1, old->DptfDisable, new->DptfDisable); |
| 195 | fsp_display_upd_value("PcdEmmcMode", 1, old->PcdEmmcMode, new->PcdEmmcMode); |
| 196 | fsp_display_upd_value("PcdUsb3ClkSsc", 1, old->PcdUsb3ClkSsc, new->PcdUsb3ClkSsc); |
| 197 | fsp_display_upd_value("PcdDispClkSsc", 1, old->PcdDispClkSsc, new->PcdDispClkSsc); |
| 198 | fsp_display_upd_value("PcdSataClkSsc", 1, old->PcdSataClkSsc, new->PcdSataClkSsc); |
| 199 | |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 200 | fsp_display_upd_value("Usb2Port0PerPortPeTxiSet", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 201 | old->Usb2Port0PerPortPeTxiSet, |
| 202 | new->Usb2Port0PerPortPeTxiSet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 203 | fsp_display_upd_value("Usb2Port0PerPortTxiSet", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 204 | old->Usb2Port0PerPortTxiSet, |
| 205 | new->Usb2Port0PerPortTxiSet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 206 | fsp_display_upd_value("Usb2Port0IUsbTxEmphasisEn", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 207 | old->Usb2Port0IUsbTxEmphasisEn, |
| 208 | new->Usb2Port0IUsbTxEmphasisEn); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 209 | fsp_display_upd_value("Usb2Port0PerPortTxPeHalf", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 210 | old->Usb2Port0PerPortTxPeHalf, |
| 211 | new->Usb2Port0PerPortTxPeHalf); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 212 | fsp_display_upd_value("Usb2Port1PerPortPeTxiSet", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 213 | old->Usb2Port1PerPortPeTxiSet, |
| 214 | new->Usb2Port1PerPortPeTxiSet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 215 | fsp_display_upd_value("Usb2Port1PerPortTxiSet", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 216 | old->Usb2Port1PerPortTxiSet, |
| 217 | new->Usb2Port1PerPortTxiSet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 218 | fsp_display_upd_value("Usb2Port1IUsbTxEmphasisEn", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 219 | old->Usb2Port1IUsbTxEmphasisEn, |
| 220 | new->Usb2Port1IUsbTxEmphasisEn); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 221 | fsp_display_upd_value("Usb2Port1PerPortTxPeHalf", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 222 | old->Usb2Port1PerPortTxPeHalf, |
| 223 | new->Usb2Port1PerPortTxPeHalf); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 224 | fsp_display_upd_value("Usb2Port2PerPortPeTxiSet", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 225 | old->Usb2Port2PerPortPeTxiSet, |
| 226 | new->Usb2Port2PerPortPeTxiSet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 227 | fsp_display_upd_value("Usb2Port2PerPortTxiSet", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 228 | old->Usb2Port2PerPortTxiSet, |
| 229 | new->Usb2Port2PerPortTxiSet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 230 | fsp_display_upd_value("Usb2Port2IUsbTxEmphasisEn", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 231 | old->Usb2Port2IUsbTxEmphasisEn, |
| 232 | new->Usb2Port2IUsbTxEmphasisEn); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 233 | fsp_display_upd_value("Usb2Port2PerPortTxPeHalf", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 234 | old->Usb2Port2PerPortTxPeHalf, |
| 235 | new->Usb2Port2PerPortTxPeHalf); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 236 | fsp_display_upd_value("Usb2Port3PerPortPeTxiSet", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 237 | old->Usb2Port3PerPortPeTxiSet, |
| 238 | new->Usb2Port3PerPortPeTxiSet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 239 | fsp_display_upd_value("Usb2Port3PerPortTxiSet", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 240 | old->Usb2Port3PerPortTxiSet, |
| 241 | new->Usb2Port3PerPortTxiSet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 242 | fsp_display_upd_value("Usb2Port3IUsbTxEmphasisEn", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 243 | old->Usb2Port3IUsbTxEmphasisEn, |
| 244 | new->Usb2Port3IUsbTxEmphasisEn); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 245 | fsp_display_upd_value("Usb2Port3PerPortTxPeHalf", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 246 | old->Usb2Port3PerPortTxPeHalf, |
| 247 | new->Usb2Port3PerPortTxPeHalf); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 248 | fsp_display_upd_value("Usb2Port4PerPortPeTxiSet", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 249 | old->Usb2Port4PerPortPeTxiSet, |
| 250 | new->Usb2Port4PerPortPeTxiSet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 251 | fsp_display_upd_value("Usb2Port4PerPortTxiSet", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 252 | old->Usb2Port4PerPortTxiSet, |
| 253 | new->Usb2Port4PerPortTxiSet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 254 | fsp_display_upd_value("Usb2Port4IUsbTxEmphasisEn", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 255 | old->Usb2Port4IUsbTxEmphasisEn, |
| 256 | new->Usb2Port4IUsbTxEmphasisEn); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 257 | fsp_display_upd_value("Usb2Port4PerPortTxPeHalf", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 258 | old->Usb2Port4PerPortTxPeHalf, |
| 259 | new->Usb2Port4PerPortTxPeHalf); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 260 | fsp_display_upd_value("Usb3Lane0Ow2tapgen2deemph3p5", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 261 | old->Usb3Lane0Ow2tapgen2deemph3p5, |
| 262 | new->Usb3Lane0Ow2tapgen2deemph3p5); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 263 | fsp_display_upd_value("Usb3Lane1Ow2tapgen2deemph3p5", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 264 | old->Usb3Lane1Ow2tapgen2deemph3p5, |
| 265 | new->Usb3Lane1Ow2tapgen2deemph3p5); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 266 | fsp_display_upd_value("Usb3Lane2Ow2tapgen2deemph3p5", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 267 | old->Usb3Lane2Ow2tapgen2deemph3p5, |
| 268 | new->Usb3Lane2Ow2tapgen2deemph3p5); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 269 | fsp_display_upd_value("Usb3Lane3Ow2tapgen2deemph3p5", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 270 | old->Usb3Lane3Ow2tapgen2deemph3p5, |
| 271 | new->Usb3Lane3Ow2tapgen2deemph3p5); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 272 | fsp_display_upd_value("PcdSataInterfaceSpeed", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 273 | old->PcdSataInterfaceSpeed, |
| 274 | new->PcdSataInterfaceSpeed); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 275 | fsp_display_upd_value("PcdPchUsbSsicPort", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 276 | old->PcdPchUsbSsicPort, |
| 277 | new->PcdPchUsbSsicPort); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 278 | fsp_display_upd_value("PcdPchUsbHsicPort", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 279 | old->PcdPchUsbHsicPort, |
| 280 | new->PcdPchUsbHsicPort); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 281 | fsp_display_upd_value("PcdPcieRootPortSpeed", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 282 | old->PcdPcieRootPortSpeed, |
| 283 | new->PcdPcieRootPortSpeed); |
| 284 | fsp_display_upd_value("PcdPchSsicEnable", 1, |
| 285 | old->PcdPchSsicEnable, |
| 286 | new->PcdPchSsicEnable); |
| 287 | |
| 288 | fsp_display_upd_value("PcdLogoPtr", 4, old->PcdLogoPtr, new->PcdLogoPtr); |
| 289 | fsp_display_upd_value("PcdLogoSize", 4, old->PcdLogoSize, new->PcdLogoSize); |
| 290 | fsp_display_upd_value("PcdRtcLock", 1, old->PcdRtcLock, new->PcdRtcLock); |
| 291 | fsp_display_upd_value("PMIC_I2CBus", 1, old->PMIC_I2CBus, new->PMIC_I2CBus); |
| 292 | fsp_display_upd_value("ISPEnable", 1, old->ISPEnable, new->ISPEnable); |
| 293 | fsp_display_upd_value("ISPPciDevConfig", 1, old->ISPPciDevConfig, new->ISPPciDevConfig); |
| 294 | fsp_display_upd_value("PcdSdDetectChk", 1, old->PcdSdDetectChk, new->PcdSdDetectChk); |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 295 | } |
| 296 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 297 | /* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */ |
| 298 | static void soc_init(void *chip_info) |
| 299 | { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 300 | soc_init_pre_device(chip_info); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 301 | } |
| 302 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 303 | struct chip_operations soc_intel_braswell_ops = { |
| 304 | CHIP_NAME("Intel Braswell SoC") |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 305 | .enable_dev = enable_dev, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 306 | .init = soc_init, |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 307 | }; |
| 308 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 309 | struct pci_operations soc_pci_ops = { |
Subrata Banik | 4a0f071 | 2019-03-20 14:29:47 +0530 | [diff] [blame] | 310 | .set_subsystem = &pci_dev_set_subsystem, |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 311 | }; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 312 | |
| 313 | /** |
| 314 | Return SoC stepping type |
| 315 | |
| 316 | @retval SOC_STEPPING SoC stepping type |
| 317 | **/ |
| 318 | int SocStepping(void) |
| 319 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 320 | struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC); |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 321 | const u8 revid = pci_read_config8(dev, 0x8); |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 322 | |
| 323 | switch (revid & B_PCH_LPC_RID_STEPPING_MASK) { |
| 324 | case V_PCH_LPC_RID_A0: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 325 | return SocA0; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 326 | case V_PCH_LPC_RID_A1: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 327 | return SocA1; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 328 | case V_PCH_LPC_RID_A2: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 329 | return SocA2; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 330 | case V_PCH_LPC_RID_A3: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 331 | return SocA3; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 332 | case V_PCH_LPC_RID_A4: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 333 | return SocA4; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 334 | case V_PCH_LPC_RID_A5: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 335 | return SocA5; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 336 | case V_PCH_LPC_RID_A6: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 337 | return SocA6; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 338 | case V_PCH_LPC_RID_A7: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 339 | return SocA7; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 340 | case V_PCH_LPC_RID_B0: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 341 | return SocB0; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 342 | case V_PCH_LPC_RID_B1: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 343 | return SocB1; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 344 | case V_PCH_LPC_RID_B2: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 345 | return SocB2; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 346 | case V_PCH_LPC_RID_B3: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 347 | return SocB3; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 348 | case V_PCH_LPC_RID_B4: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 349 | return SocB4; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 350 | case V_PCH_LPC_RID_B5: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 351 | return SocB5; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 352 | case V_PCH_LPC_RID_B6: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 353 | return SocB6; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 354 | case V_PCH_LPC_RID_B7: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 355 | return SocB7; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 356 | case V_PCH_LPC_RID_C0: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 357 | return SocC0; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 358 | case V_PCH_LPC_RID_C1: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 359 | return SocC1; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 360 | case V_PCH_LPC_RID_C2: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 361 | return SocC2; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 362 | case V_PCH_LPC_RID_C3: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 363 | return SocC3; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 364 | case V_PCH_LPC_RID_C4: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 365 | return SocC4; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 366 | case V_PCH_LPC_RID_C5: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 367 | return SocC5; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 368 | case V_PCH_LPC_RID_C6: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 369 | return SocC6; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 370 | case V_PCH_LPC_RID_C7: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 371 | return SocC7; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 372 | case V_PCH_LPC_RID_D0: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 373 | return SocD0; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 374 | case V_PCH_LPC_RID_D1: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 375 | return SocD1; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 376 | case V_PCH_LPC_RID_D2: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 377 | return SocD2; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 378 | case V_PCH_LPC_RID_D3: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 379 | return SocD3; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 380 | case V_PCH_LPC_RID_D4: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 381 | return SocD4; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 382 | case V_PCH_LPC_RID_D5: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 383 | return SocD5; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 384 | case V_PCH_LPC_RID_D6: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 385 | return SocD6; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 386 | case V_PCH_LPC_RID_D7: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 387 | return SocD7; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 388 | default: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 389 | return SocSteppingMax; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 390 | } |
| 391 | } |