Angel Pons | ba38f37 | 2020-04-05 15:46:45 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 3 | |
| 4 | #include <console/console.h> |
| 5 | #include <device/device.h> |
| 6 | #include <device/pci.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 7 | #include <device/pci_ops.h> |
Aaron Durbin | 789f2b6 | 2015-09-09 17:05:06 -0500 | [diff] [blame] | 8 | #include <fsp/util.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 9 | #include <soc/pci_devs.h> |
| 10 | #include <soc/ramstage.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 11 | |
Elyes HAOUAS | c338507 | 2019-03-21 15:38:06 +0100 | [diff] [blame] | 12 | #include "chip.h" |
| 13 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 14 | static void pci_domain_set_resources(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 15 | { |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 16 | printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 17 | assign_resources(dev->link_list); |
| 18 | } |
| 19 | |
| 20 | static struct device_operations pci_domain_ops = { |
| 21 | .read_resources = pci_domain_read_resources, |
| 22 | .set_resources = pci_domain_set_resources, |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 23 | .scan_bus = pci_domain_scan_bus, |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 24 | }; |
| 25 | |
| 26 | static struct device_operations cpu_bus_ops = { |
Elyes HAOUAS | b6fa7a2 | 2018-12-07 12:21:18 +0100 | [diff] [blame] | 27 | .read_resources = DEVICE_NOOP, |
| 28 | .set_resources = DEVICE_NOOP, |
| 29 | .enable_resources = DEVICE_NOOP, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 30 | .init = soc_init_cpus |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 31 | }; |
| 32 | |
| 33 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 34 | static void enable_dev(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 35 | { |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 36 | printk(BIOS_SPEW, "----------\n%s/%s (%s), type: %d\n", __FILE__, __func__, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 37 | dev_name(dev), dev->path.type); |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 38 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 39 | printk(BIOS_SPEW, "vendor: 0x%04x. device: 0x%04x\n", |
| 40 | pci_read_config16(dev, PCI_VENDOR_ID), |
| 41 | pci_read_config16(dev, PCI_DEVICE_ID)); |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 42 | |
| 43 | printk(BIOS_SPEW, "class: 0x%02x %s\nsubclass: 0x%02x %s\n" |
| 44 | "prog: 0x%02x\nrevision: 0x%02x\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 45 | pci_read_config16(dev, PCI_CLASS_DEVICE) >> 8, |
| 46 | get_pci_class_name(dev), |
| 47 | pci_read_config16(dev, PCI_CLASS_DEVICE) & 0xff, |
| 48 | get_pci_subclass_name(dev), |
| 49 | pci_read_config8(dev, PCI_CLASS_PROG), |
| 50 | pci_read_config8(dev, PCI_REVISION_ID)); |
| 51 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 52 | /* Set the operations if it is a special bus type */ |
| 53 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 54 | dev->ops = &pci_domain_ops; |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 55 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 56 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 57 | dev->ops = &cpu_bus_ops; |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 58 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 59 | } else if (dev->path.type == DEVICE_PATH_PCI) { |
| 60 | /* Handle south cluster enablement. */ |
| 61 | if (PCI_SLOT(dev->path.pci.devfn) > GFX_DEV && |
| 62 | (dev->ops == NULL || dev->ops->enable == NULL)) { |
| 63 | southcluster_enable_dev(dev); |
| 64 | } |
| 65 | } |
| 66 | } |
| 67 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 68 | __weak void board_silicon_USB2_override(SILICON_INIT_UPD *params) |
Matt DeVillier | 2c8ac22 | 2017-08-26 04:53:35 -0500 | [diff] [blame] | 69 | { |
| 70 | } |
| 71 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 72 | void soc_silicon_init_params(SILICON_INIT_UPD *params) |
| 73 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 74 | struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC); |
Ravi Sarawadi | d077b58 | 2015-09-09 14:12:16 -0700 | [diff] [blame] | 75 | struct soc_intel_braswell_config *config; |
| 76 | |
| 77 | if (!dev) { |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 78 | printk(BIOS_ERR, "Error! Device (%s) not found, soc_silicon_init_params!\n", |
| 79 | dev_path(dev)); |
Ravi Sarawadi | d077b58 | 2015-09-09 14:12:16 -0700 | [diff] [blame] | 80 | return; |
| 81 | } |
| 82 | |
Kyösti Mälkki | 8950cfb | 2019-07-13 22:16:25 +0300 | [diff] [blame] | 83 | config = config_of(dev); |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 84 | |
| 85 | /* Set the parameters for SiliconInit */ |
| 86 | printk(BIOS_DEBUG, "Updating UPD values for SiliconInit\n"); |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 87 | params->PcdSdcardMode = config->PcdSdcardMode; |
| 88 | params->PcdEnableHsuart0 = config->PcdEnableHsuart0; |
| 89 | params->PcdEnableHsuart1 = config->PcdEnableHsuart1; |
| 90 | params->PcdEnableAzalia = config->PcdEnableAzalia; |
| 91 | params->PcdEnableSata = config->PcdEnableSata; |
| 92 | params->PcdEnableXhci = config->PcdEnableXhci; |
| 93 | params->PcdEnableLpe = config->PcdEnableLpe; |
| 94 | params->PcdEnableDma0 = config->PcdEnableDma0; |
| 95 | params->PcdEnableDma1 = config->PcdEnableDma1; |
| 96 | params->PcdEnableI2C0 = config->PcdEnableI2C0; |
| 97 | params->PcdEnableI2C1 = config->PcdEnableI2C1; |
| 98 | params->PcdEnableI2C2 = config->PcdEnableI2C2; |
| 99 | params->PcdEnableI2C3 = config->PcdEnableI2C3; |
| 100 | params->PcdEnableI2C4 = config->PcdEnableI2C4; |
| 101 | params->PcdEnableI2C5 = config->PcdEnableI2C5; |
| 102 | params->PcdEnableI2C6 = config->PcdEnableI2C6; |
| 103 | params->GraphicsConfigPtr = 0; |
| 104 | params->AzaliaConfigPtr = 0; |
| 105 | params->PunitPwrConfigDisable = config->PunitPwrConfigDisable; |
| 106 | params->ChvSvidConfig = config->ChvSvidConfig; |
| 107 | params->DptfDisable = config->DptfDisable; |
| 108 | params->PcdEmmcMode = config->PcdEmmcMode; |
| 109 | params->PcdUsb3ClkSsc = config->PcdUsb3ClkSsc; |
| 110 | params->PcdDispClkSsc = config->PcdDispClkSsc; |
| 111 | params->PcdSataClkSsc = config->PcdSataClkSsc; |
Kevin Chiu | 348a6d5 | 2016-06-30 14:50:52 +0800 | [diff] [blame] | 112 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 113 | params->Usb2Port0PerPortPeTxiSet = config->Usb2Port0PerPortPeTxiSet; |
| 114 | params->Usb2Port0PerPortTxiSet = config->Usb2Port0PerPortTxiSet; |
| 115 | params->Usb2Port0IUsbTxEmphasisEn = config->Usb2Port0IUsbTxEmphasisEn; |
| 116 | params->Usb2Port0PerPortTxPeHalf = config->Usb2Port0PerPortTxPeHalf; |
Kevin Chiu | 348a6d5 | 2016-06-30 14:50:52 +0800 | [diff] [blame] | 117 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 118 | params->Usb2Port1PerPortPeTxiSet = config->Usb2Port1PerPortPeTxiSet; |
| 119 | params->Usb2Port1PerPortTxiSet = config->Usb2Port1PerPortTxiSet; |
| 120 | params->Usb2Port1IUsbTxEmphasisEn = config->Usb2Port1IUsbTxEmphasisEn; |
| 121 | params->Usb2Port1PerPortTxPeHalf = config->Usb2Port1PerPortTxPeHalf; |
Kevin Chiu | 348a6d5 | 2016-06-30 14:50:52 +0800 | [diff] [blame] | 122 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 123 | params->Usb2Port2PerPortPeTxiSet = config->Usb2Port2PerPortPeTxiSet; |
| 124 | params->Usb2Port2PerPortTxiSet = config->Usb2Port2PerPortTxiSet; |
| 125 | params->Usb2Port2IUsbTxEmphasisEn = config->Usb2Port2IUsbTxEmphasisEn; |
| 126 | params->Usb2Port2PerPortTxPeHalf = config->Usb2Port2PerPortTxPeHalf; |
Kevin Chiu | 348a6d5 | 2016-06-30 14:50:52 +0800 | [diff] [blame] | 127 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 128 | params->Usb2Port3PerPortPeTxiSet = config->Usb2Port3PerPortPeTxiSet; |
| 129 | params->Usb2Port3PerPortTxiSet = config->Usb2Port3PerPortTxiSet; |
| 130 | params->Usb2Port3IUsbTxEmphasisEn = config->Usb2Port3IUsbTxEmphasisEn; |
| 131 | params->Usb2Port3PerPortTxPeHalf = config->Usb2Port3PerPortTxPeHalf; |
Kevin Chiu | 348a6d5 | 2016-06-30 14:50:52 +0800 | [diff] [blame] | 132 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 133 | params->Usb2Port4PerPortPeTxiSet = config->Usb2Port4PerPortPeTxiSet; |
| 134 | params->Usb2Port4PerPortTxiSet = config->Usb2Port4PerPortTxiSet; |
| 135 | params->Usb2Port4IUsbTxEmphasisEn = config->Usb2Port4IUsbTxEmphasisEn; |
| 136 | params->Usb2Port4PerPortTxPeHalf = config->Usb2Port4PerPortTxPeHalf; |
| 137 | |
| 138 | params->Usb3Lane0Ow2tapgen2deemph3p5 = config->Usb3Lane0Ow2tapgen2deemph3p5; |
| 139 | params->Usb3Lane1Ow2tapgen2deemph3p5 = config->Usb3Lane1Ow2tapgen2deemph3p5; |
| 140 | params->Usb3Lane2Ow2tapgen2deemph3p5 = config->Usb3Lane2Ow2tapgen2deemph3p5; |
| 141 | params->Usb3Lane3Ow2tapgen2deemph3p5 = config->Usb3Lane3Ow2tapgen2deemph3p5; |
| 142 | |
| 143 | params->PcdSataInterfaceSpeed = config->PcdSataInterfaceSpeed; |
| 144 | params->PcdPchUsbSsicPort = config->PcdPchUsbSsicPort; |
| 145 | params->PcdPchUsbHsicPort = config->PcdPchUsbHsicPort; |
| 146 | params->PcdPcieRootPortSpeed = config->PcdPcieRootPortSpeed; |
| 147 | params->PcdPchSsicEnable = config->PcdPchSsicEnable; |
| 148 | params->PcdLogoPtr = config->PcdLogoPtr; |
| 149 | params->PcdLogoSize = config->PcdLogoSize; |
| 150 | params->PcdRtcLock = config->PcdRtcLock; |
| 151 | params->PMIC_I2CBus = config->PMIC_I2CBus; |
| 152 | params->ISPEnable = config->ISPEnable; |
| 153 | params->ISPPciDevConfig = config->ISPPciDevConfig; |
| 154 | params->PcdSdDetectChk = config->PcdSdDetectChk; |
| 155 | params->I2C0Frequency = config->I2C0Frequency; |
| 156 | params->I2C1Frequency = config->I2C1Frequency; |
| 157 | params->I2C2Frequency = config->I2C2Frequency; |
| 158 | params->I2C3Frequency = config->I2C3Frequency; |
| 159 | params->I2C4Frequency = config->I2C4Frequency; |
| 160 | params->I2C5Frequency = config->I2C5Frequency; |
| 161 | params->I2C6Frequency = config->I2C6Frequency; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 162 | |
Matt DeVillier | 2c8ac22 | 2017-08-26 04:53:35 -0500 | [diff] [blame] | 163 | board_silicon_USB2_override(params); |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 164 | } |
| 165 | |
Wim Vervoorn | 67117c3 | 2019-12-16 14:21:09 +0100 | [diff] [blame] | 166 | const struct cbmem_entry *soc_load_logo(SILICON_INIT_UPD *params) |
| 167 | { |
| 168 | return fsp_load_logo(¶ms->PcdLogoPtr, ¶ms->PcdLogoSize); |
| 169 | } |
| 170 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 171 | void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, SILICON_INIT_UPD *new) |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 172 | { |
| 173 | /* Display the parameters for SiliconInit */ |
| 174 | printk(BIOS_SPEW, "UPD values for SiliconInit:\n"); |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 175 | |
| 176 | fsp_display_upd_value("PcdSdcardMode", 1, |
| 177 | old->PcdSdcardMode, |
| 178 | new->PcdSdcardMode); |
| 179 | fsp_display_upd_value("PcdEnableHsuart0", 1, |
| 180 | old->PcdEnableHsuart0, |
| 181 | new->PcdEnableHsuart0); |
| 182 | fsp_display_upd_value("PcdEnableHsuart1", 1, |
| 183 | old->PcdEnableHsuart1, |
| 184 | new->PcdEnableHsuart1); |
| 185 | fsp_display_upd_value("PcdEnableAzalia", 1, |
| 186 | old->PcdEnableAzalia, |
| 187 | new->PcdEnableAzalia); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 188 | fsp_display_upd_value("AzaliaConfigPtr", 4, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 189 | (uint32_t)old->AzaliaConfigPtr, |
| 190 | (uint32_t)new->AzaliaConfigPtr); |
| 191 | |
| 192 | fsp_display_upd_value("PcdEnableSata", 1, old->PcdEnableSata, new->PcdEnableSata); |
| 193 | fsp_display_upd_value("PcdEnableXhci", 1, old->PcdEnableXhci, new->PcdEnableXhci); |
| 194 | fsp_display_upd_value("PcdEnableLpe", 1, old->PcdEnableLpe, new->PcdEnableLpe); |
| 195 | fsp_display_upd_value("PcdEnableDma0", 1, old->PcdEnableDma0, new->PcdEnableDma0); |
| 196 | fsp_display_upd_value("PcdEnableDma1", 1, old->PcdEnableDma1, new->PcdEnableDma1); |
| 197 | fsp_display_upd_value("PcdEnableI2C0", 1, old->PcdEnableI2C0, new->PcdEnableI2C0); |
| 198 | fsp_display_upd_value("PcdEnableI2C1", 1, old->PcdEnableI2C1, new->PcdEnableI2C1); |
| 199 | fsp_display_upd_value("PcdEnableI2C2", 1, old->PcdEnableI2C2, new->PcdEnableI2C2); |
| 200 | fsp_display_upd_value("PcdEnableI2C3", 1, old->PcdEnableI2C3, new->PcdEnableI2C3); |
| 201 | fsp_display_upd_value("PcdEnableI2C4", 1, old->PcdEnableI2C4, new->PcdEnableI2C4); |
| 202 | fsp_display_upd_value("PcdEnableI2C5", 1, old->PcdEnableI2C5, new->PcdEnableI2C5); |
| 203 | fsp_display_upd_value("PcdEnableI2C6", 1, old->PcdEnableI2C6, new->PcdEnableI2C6); |
| 204 | |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 205 | fsp_display_upd_value("PcdGraphicsConfigPtr", 4, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 206 | old->GraphicsConfigPtr, |
| 207 | new->GraphicsConfigPtr); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 208 | fsp_display_upd_value("GpioFamilyInitTablePtr", 4, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 209 | (uint32_t)old->GpioFamilyInitTablePtr, |
| 210 | (uint32_t)new->GpioFamilyInitTablePtr); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 211 | fsp_display_upd_value("GpioPadInitTablePtr", 4, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 212 | (uint32_t)old->GpioPadInitTablePtr, |
| 213 | (uint32_t)new->GpioPadInitTablePtr); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 214 | fsp_display_upd_value("PunitPwrConfigDisable", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 215 | old->PunitPwrConfigDisable, |
| 216 | new->PunitPwrConfigDisable); |
| 217 | |
| 218 | fsp_display_upd_value("ChvSvidConfig", 1, old->ChvSvidConfig, new->ChvSvidConfig); |
| 219 | fsp_display_upd_value("DptfDisable", 1, old->DptfDisable, new->DptfDisable); |
| 220 | fsp_display_upd_value("PcdEmmcMode", 1, old->PcdEmmcMode, new->PcdEmmcMode); |
| 221 | fsp_display_upd_value("PcdUsb3ClkSsc", 1, old->PcdUsb3ClkSsc, new->PcdUsb3ClkSsc); |
| 222 | fsp_display_upd_value("PcdDispClkSsc", 1, old->PcdDispClkSsc, new->PcdDispClkSsc); |
| 223 | fsp_display_upd_value("PcdSataClkSsc", 1, old->PcdSataClkSsc, new->PcdSataClkSsc); |
| 224 | |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 225 | fsp_display_upd_value("Usb2Port0PerPortPeTxiSet", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 226 | old->Usb2Port0PerPortPeTxiSet, |
| 227 | new->Usb2Port0PerPortPeTxiSet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 228 | fsp_display_upd_value("Usb2Port0PerPortTxiSet", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 229 | old->Usb2Port0PerPortTxiSet, |
| 230 | new->Usb2Port0PerPortTxiSet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 231 | fsp_display_upd_value("Usb2Port0IUsbTxEmphasisEn", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 232 | old->Usb2Port0IUsbTxEmphasisEn, |
| 233 | new->Usb2Port0IUsbTxEmphasisEn); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 234 | fsp_display_upd_value("Usb2Port0PerPortTxPeHalf", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 235 | old->Usb2Port0PerPortTxPeHalf, |
| 236 | new->Usb2Port0PerPortTxPeHalf); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 237 | fsp_display_upd_value("Usb2Port1PerPortPeTxiSet", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 238 | old->Usb2Port1PerPortPeTxiSet, |
| 239 | new->Usb2Port1PerPortPeTxiSet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 240 | fsp_display_upd_value("Usb2Port1PerPortTxiSet", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 241 | old->Usb2Port1PerPortTxiSet, |
| 242 | new->Usb2Port1PerPortTxiSet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 243 | fsp_display_upd_value("Usb2Port1IUsbTxEmphasisEn", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 244 | old->Usb2Port1IUsbTxEmphasisEn, |
| 245 | new->Usb2Port1IUsbTxEmphasisEn); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 246 | fsp_display_upd_value("Usb2Port1PerPortTxPeHalf", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 247 | old->Usb2Port1PerPortTxPeHalf, |
| 248 | new->Usb2Port1PerPortTxPeHalf); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 249 | fsp_display_upd_value("Usb2Port2PerPortPeTxiSet", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 250 | old->Usb2Port2PerPortPeTxiSet, |
| 251 | new->Usb2Port2PerPortPeTxiSet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 252 | fsp_display_upd_value("Usb2Port2PerPortTxiSet", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 253 | old->Usb2Port2PerPortTxiSet, |
| 254 | new->Usb2Port2PerPortTxiSet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 255 | fsp_display_upd_value("Usb2Port2IUsbTxEmphasisEn", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 256 | old->Usb2Port2IUsbTxEmphasisEn, |
| 257 | new->Usb2Port2IUsbTxEmphasisEn); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 258 | fsp_display_upd_value("Usb2Port2PerPortTxPeHalf", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 259 | old->Usb2Port2PerPortTxPeHalf, |
| 260 | new->Usb2Port2PerPortTxPeHalf); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 261 | fsp_display_upd_value("Usb2Port3PerPortPeTxiSet", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 262 | old->Usb2Port3PerPortPeTxiSet, |
| 263 | new->Usb2Port3PerPortPeTxiSet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 264 | fsp_display_upd_value("Usb2Port3PerPortTxiSet", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 265 | old->Usb2Port3PerPortTxiSet, |
| 266 | new->Usb2Port3PerPortTxiSet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 267 | fsp_display_upd_value("Usb2Port3IUsbTxEmphasisEn", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 268 | old->Usb2Port3IUsbTxEmphasisEn, |
| 269 | new->Usb2Port3IUsbTxEmphasisEn); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 270 | fsp_display_upd_value("Usb2Port3PerPortTxPeHalf", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 271 | old->Usb2Port3PerPortTxPeHalf, |
| 272 | new->Usb2Port3PerPortTxPeHalf); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 273 | fsp_display_upd_value("Usb2Port4PerPortPeTxiSet", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 274 | old->Usb2Port4PerPortPeTxiSet, |
| 275 | new->Usb2Port4PerPortPeTxiSet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 276 | fsp_display_upd_value("Usb2Port4PerPortTxiSet", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 277 | old->Usb2Port4PerPortTxiSet, |
| 278 | new->Usb2Port4PerPortTxiSet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 279 | fsp_display_upd_value("Usb2Port4IUsbTxEmphasisEn", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 280 | old->Usb2Port4IUsbTxEmphasisEn, |
| 281 | new->Usb2Port4IUsbTxEmphasisEn); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 282 | fsp_display_upd_value("Usb2Port4PerPortTxPeHalf", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 283 | old->Usb2Port4PerPortTxPeHalf, |
| 284 | new->Usb2Port4PerPortTxPeHalf); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 285 | fsp_display_upd_value("Usb3Lane0Ow2tapgen2deemph3p5", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 286 | old->Usb3Lane0Ow2tapgen2deemph3p5, |
| 287 | new->Usb3Lane0Ow2tapgen2deemph3p5); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 288 | fsp_display_upd_value("Usb3Lane1Ow2tapgen2deemph3p5", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 289 | old->Usb3Lane1Ow2tapgen2deemph3p5, |
| 290 | new->Usb3Lane1Ow2tapgen2deemph3p5); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 291 | fsp_display_upd_value("Usb3Lane2Ow2tapgen2deemph3p5", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 292 | old->Usb3Lane2Ow2tapgen2deemph3p5, |
| 293 | new->Usb3Lane2Ow2tapgen2deemph3p5); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 294 | fsp_display_upd_value("Usb3Lane3Ow2tapgen2deemph3p5", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 295 | old->Usb3Lane3Ow2tapgen2deemph3p5, |
| 296 | new->Usb3Lane3Ow2tapgen2deemph3p5); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 297 | fsp_display_upd_value("PcdSataInterfaceSpeed", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 298 | old->PcdSataInterfaceSpeed, |
| 299 | new->PcdSataInterfaceSpeed); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 300 | fsp_display_upd_value("PcdPchUsbSsicPort", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 301 | old->PcdPchUsbSsicPort, |
| 302 | new->PcdPchUsbSsicPort); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 303 | fsp_display_upd_value("PcdPchUsbHsicPort", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 304 | old->PcdPchUsbHsicPort, |
| 305 | new->PcdPchUsbHsicPort); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 306 | fsp_display_upd_value("PcdPcieRootPortSpeed", 1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 307 | old->PcdPcieRootPortSpeed, |
| 308 | new->PcdPcieRootPortSpeed); |
| 309 | fsp_display_upd_value("PcdPchSsicEnable", 1, |
| 310 | old->PcdPchSsicEnable, |
| 311 | new->PcdPchSsicEnable); |
| 312 | |
| 313 | fsp_display_upd_value("PcdLogoPtr", 4, old->PcdLogoPtr, new->PcdLogoPtr); |
| 314 | fsp_display_upd_value("PcdLogoSize", 4, old->PcdLogoSize, new->PcdLogoSize); |
| 315 | fsp_display_upd_value("PcdRtcLock", 1, old->PcdRtcLock, new->PcdRtcLock); |
| 316 | fsp_display_upd_value("PMIC_I2CBus", 1, old->PMIC_I2CBus, new->PMIC_I2CBus); |
| 317 | fsp_display_upd_value("ISPEnable", 1, old->ISPEnable, new->ISPEnable); |
| 318 | fsp_display_upd_value("ISPPciDevConfig", 1, old->ISPPciDevConfig, new->ISPPciDevConfig); |
| 319 | fsp_display_upd_value("PcdSdDetectChk", 1, old->PcdSdDetectChk, new->PcdSdDetectChk); |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 320 | } |
| 321 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 322 | /* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */ |
| 323 | static void soc_init(void *chip_info) |
| 324 | { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 325 | printk(BIOS_SPEW, "%s/%s\n", __FILE__, __func__); |
| 326 | soc_init_pre_device(chip_info); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 327 | } |
| 328 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 329 | struct chip_operations soc_intel_braswell_ops = { |
| 330 | CHIP_NAME("Intel Braswell SoC") |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 331 | .enable_dev = enable_dev, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 332 | .init = soc_init, |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 333 | }; |
| 334 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 335 | struct pci_operations soc_pci_ops = { |
Subrata Banik | 4a0f071 | 2019-03-20 14:29:47 +0530 | [diff] [blame] | 336 | .set_subsystem = &pci_dev_set_subsystem, |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 337 | }; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 338 | |
| 339 | /** |
| 340 | Return SoC stepping type |
| 341 | |
| 342 | @retval SOC_STEPPING SoC stepping type |
| 343 | **/ |
| 344 | int SocStepping(void) |
| 345 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 346 | struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC); |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 347 | const u8 revid = pci_read_config8(dev, 0x8); |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 348 | |
| 349 | switch (revid & B_PCH_LPC_RID_STEPPING_MASK) { |
| 350 | case V_PCH_LPC_RID_A0: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 351 | return SocA0; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 352 | case V_PCH_LPC_RID_A1: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 353 | return SocA1; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 354 | case V_PCH_LPC_RID_A2: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 355 | return SocA2; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 356 | case V_PCH_LPC_RID_A3: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 357 | return SocA3; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 358 | case V_PCH_LPC_RID_A4: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 359 | return SocA4; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 360 | case V_PCH_LPC_RID_A5: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 361 | return SocA5; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 362 | case V_PCH_LPC_RID_A6: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 363 | return SocA6; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 364 | case V_PCH_LPC_RID_A7: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 365 | return SocA7; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 366 | case V_PCH_LPC_RID_B0: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 367 | return SocB0; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 368 | case V_PCH_LPC_RID_B1: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 369 | return SocB1; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 370 | case V_PCH_LPC_RID_B2: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 371 | return SocB2; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 372 | case V_PCH_LPC_RID_B3: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 373 | return SocB3; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 374 | case V_PCH_LPC_RID_B4: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 375 | return SocB4; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 376 | case V_PCH_LPC_RID_B5: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 377 | return SocB5; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 378 | case V_PCH_LPC_RID_B6: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 379 | return SocB6; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 380 | case V_PCH_LPC_RID_B7: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 381 | return SocB7; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 382 | case V_PCH_LPC_RID_C0: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 383 | return SocC0; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 384 | case V_PCH_LPC_RID_C1: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 385 | return SocC1; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 386 | case V_PCH_LPC_RID_C2: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 387 | return SocC2; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 388 | case V_PCH_LPC_RID_C3: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 389 | return SocC3; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 390 | case V_PCH_LPC_RID_C4: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 391 | return SocC4; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 392 | case V_PCH_LPC_RID_C5: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 393 | return SocC5; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 394 | case V_PCH_LPC_RID_C6: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 395 | return SocC6; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 396 | case V_PCH_LPC_RID_C7: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 397 | return SocC7; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 398 | case V_PCH_LPC_RID_D0: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 399 | return SocD0; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 400 | case V_PCH_LPC_RID_D1: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 401 | return SocD1; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 402 | case V_PCH_LPC_RID_D2: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 403 | return SocD2; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 404 | case V_PCH_LPC_RID_D3: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 405 | return SocD3; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 406 | case V_PCH_LPC_RID_D4: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 407 | return SocD4; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 408 | case V_PCH_LPC_RID_D5: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 409 | return SocD5; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 410 | case V_PCH_LPC_RID_D6: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 411 | return SocD6; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 412 | case V_PCH_LPC_RID_D7: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 413 | return SocD7; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 414 | default: |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 415 | return SocSteppingMax; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 416 | } |
| 417 | } |