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review.coreboot.org / coreboot / b70ff52b83d5ffe9feca95d086a5366dd6f6ce4d / . / src / southbridge / intel / i82801gx / acpi / ich7.asl
blob: 6c9c9694f9c9278cd8bad1588e8cbce8811547bf [file] [log] [blame]
Angel Pons182dbde2020-04-02 23:49:05 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]2
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame]3/* Intel 82801Gx support */
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]4
Elyes HAOUAS484efff2018-12-20 08:46:02 +0100[diff] [blame]5#include "../i82801gx.h"
6
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]7Scope(\)
8{
9 // IO-Trap at 0x800. This is the ACPI->SMI communication interface.
10
11 OperationRegion(IO_T, SystemIO, 0x800, 0x10)
12 Field(IO_T, ByteAcc, NoLock, Preserve)
13 {
14 Offset(0x8),
15 TRP0, 8 // IO-Trap at 0x808
16 }
17
18 // ICH7 Power Management Registers, located at PMBASE (0x1f.0 0x40.l)
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame]19 OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80)
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]20 Field(PMIO, ByteAcc, NoLock, Preserve)
21 {
22 Offset(0x42), // General Purpose Control
23 , 1, // skip 1 bit
24 GPEC, 1, // TCO status
25 , 9, // skip 9 more bits
26 SCIS, 1, // TCO DMI status
27 , 6 // To the end of the word
28 }
29
30 // ICH7 GPIO IO mapped registers (0x1f.0 reg 0x48.l)
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame]31 OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x3c)
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]32 Field(GPIO, ByteAcc, NoLock, Preserve)
33 {
Elyes HAOUAS80505a62019-03-01 11:07:06 +0100[diff] [blame]34 // GPIO Use Select
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]35 GU00, 8,
36 GU01, 8,
37 GU02, 8,
38 GU03, 8,
Elyes HAOUAS80505a62019-03-01 11:07:06 +0100[diff] [blame]39 // GPIO IO Select
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]40 GIO0, 8,
41 GIO1, 8,
42 GIO2, 8,
43 GIO3, 8,
44 Offset(0x0c), // GPIO Level
Sven Schnelle8a539b62011-04-01 07:28:35 +0000[diff] [blame]45 GP00, 1,
46 GP01, 1,
47 GP02, 1,
48 GP03, 1,
49 GP04, 1,
50 GP05, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]51 GP06, 1,
Sven Schnelle8a539b62011-04-01 07:28:35 +0000[diff] [blame]52 GP07, 1,
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame]53 GP08, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]54 GP09, 1,
55 GP10, 1,
Sven Schnelle8a539b62011-04-01 07:28:35 +0000[diff] [blame]56 GP11, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]57 GP12, 1,
58 GP13, 1,
59 GP14, 1,
60 GP15, 1,
Sven Schnelle8a539b62011-04-01 07:28:35 +0000[diff] [blame]61 GP16, 1,
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame]62 GP17, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]63 GP18, 1,
64 GP19, 1,
65 GP20, 1,
Sven Schnelle8a539b62011-04-01 07:28:35 +0000[diff] [blame]66 GP21, 1,
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame]67 GP22, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]68 GP23, 1,
69 GP24, 1,
70 GP25, 1,
71 GP26, 1,
72 GP27, 1,
Sven Schnelle8a539b62011-04-01 07:28:35 +0000[diff] [blame]73 GP28, 1,
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame]74 GP29, 1,
75 GP30, 1,
76 GP31, 1,
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]77 Offset(0x18), // GPIO Blink
78 GB00, 8,
79 GB01, 8,
80 GB02, 8,
81 GB03, 8,
82 Offset(0x2c), // GPIO Invert
83 GIV0, 8,
84 GIV1, 8,
85 GIV2, 8,
86 GIV3, 8,
Elyes HAOUAS80505a62019-03-01 11:07:06 +0100[diff] [blame]87 // GPIO Use Select 2
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]88 GU04, 8,
89 GU05, 8,
90 GU06, 8,
91 GU07, 8,
Elyes HAOUAS80505a62019-03-01 11:07:06 +0100[diff] [blame]92 // GPIO IO Select 2
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]93 GIO4, 8,
94 GIO5, 8,
95 GIO6, 8,
96 GIO7, 8,
Elyes HAOUAS80505a62019-03-01 11:07:06 +0100[diff] [blame]97 // GPIO Level 2
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame]98 GP32, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]99 GP33, 1,
100 GP34, 1,
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame]101 GP35, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]102 GP36, 1,
103 GP37, 1,
104 GP38, 1,
105 GP39, 1,
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]106 GL05, 8,
107 GL06, 8,
108 GL07, 8
109 }
110
111
112 // ICH7 Root Complex Register Block. Memory Mapped through RCBA)
Angel Ponsb70ff522021-01-28 14:27:46 +0100[diff] [blame^]113 OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]114 Field(RCRB, DWordAcc, Lock, Preserve)
115 {
Elyes HAOUAS80505a62019-03-01 11:07:06 +0100[diff] [blame]116 // Backbone
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]117 Offset(0x1000), // Chipset
118 Offset(0x3000), // Legacy Configuration Registers
119 Offset(0x3404), // High Performance Timer Configuration
Elyes HAOUASb0f19882018-06-09 11:59:00 +0200[diff] [blame]120 HPAS, 2, // Address Select
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]121 , 5,
122 HPTE, 1, // Address Enable
123 Offset(0x3418), // FD (Function Disable)
Stefan Reinauer573f7d42009-07-21 21:50:34 +0000[diff] [blame]124 , 1, // Reserved
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]125 PATD, 1, // PATA disable
126 SATD, 1, // SATA disable
127 SMBD, 1, // SMBUS disable
128 HDAD, 1, // Azalia disable
Stefan Reinauer573f7d42009-07-21 21:50:34 +0000[diff] [blame]129 A97D, 1, // AC'97 disable
130 M97D, 1, // AC'97 disable
131 ILND, 1, // Internal LAN disable
132 US1D, 1, // UHCI #1 disable
133 US2D, 1, // UHCI #2 disable
134 US3D, 1, // UHCI #3 disable
135 US4D, 1, // UHCI #4 disable
136 , 2, // Reserved
137 LPBD, 1, // LPC bridge disable
138 EHCD, 1, // EHCI disable
Elyes HAOUAS80505a62019-03-01 11:07:06 +0100[diff] [blame]139 // FD Root Ports
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]140 RP1D, 1, // Root Port 1 disable
141 RP2D, 1, // Root Port 2 disable
142 RP3D, 1, // Root Port 3 disable
143 RP4D, 1, // Root Port 4 disable
144 RP5D, 1, // Root Port 5 disable
145 RP6D, 1 // Root Port 6 disable
146 }
Stefan Reinauer109ab312009-08-12 16:08:05 +0000[diff] [blame]147
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]148}
149
150// 0:1b.0 High Definition Audio (Azalia)
Angel Ponsb6427b02020-07-07 01:29:40 +0200[diff] [blame]151#include <southbridge/intel/common/acpi/audio_ich.asl>
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]152
153// PCI Express Ports
Arthur Heymansdff185a2018-12-30 12:59:39 +0100[diff] [blame]154#include <southbridge/intel/common/acpi/pcie.asl>
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]155
156// USB
Patrick Georgi334328a2012-02-16 19:01:22 +0100[diff] [blame]157#include "usb.asl"
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]158
159// PCI Bridge
Patrick Georgi334328a2012-02-16 19:01:22 +0100[diff] [blame]160#include "pci.asl"
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]161
Stefan Reinauer573f7d42009-07-21 21:50:34 +0000[diff] [blame]162// AC97 Audio and Modem
Patrick Georgi334328a2012-02-16 19:01:22 +0100[diff] [blame]163#include "ac97.asl"
Stefan Reinauer573f7d42009-07-21 21:50:34 +0000[diff] [blame]164
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]165// LPC Bridge
Patrick Georgi334328a2012-02-16 19:01:22 +0100[diff] [blame]166#include "lpc.asl"
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]167
168// PATA
Patrick Georgi334328a2012-02-16 19:01:22 +0100[diff] [blame]169#include "pata.asl"
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]170
171// SATA
Patrick Georgi334328a2012-02-16 19:01:22 +0100[diff] [blame]172#include "sata.asl"
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]173
174// SMBus
Elyes HAOUAS085ab5a2019-10-31 10:12:02 +0100[diff] [blame]175#include <southbridge/intel/common/acpi/smbus.asl>