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review.coreboot.org / coreboot / b0f1988f893bf5f581917816b11e810309955143 / . / src / southbridge / intel / i82801gx / acpi / ich7.asl
blob: cf158df7297686190aebe7d402bed4f408e82db1 [file] [log] [blame]
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]15 */
16
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame]17/* Intel 82801Gx support */
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]18
19Scope(\)
20{
21 // IO-Trap at 0x800. This is the ACPI->SMI communication interface.
22
23 OperationRegion(IO_T, SystemIO, 0x800, 0x10)
24 Field(IO_T, ByteAcc, NoLock, Preserve)
25 {
26 Offset(0x8),
27 TRP0, 8 // IO-Trap at 0x808
28 }
29
30 // ICH7 Power Management Registers, located at PMBASE (0x1f.0 0x40.l)
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame]31 OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80)
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]32 Field(PMIO, ByteAcc, NoLock, Preserve)
33 {
34 Offset(0x42), // General Purpose Control
35 , 1, // skip 1 bit
36 GPEC, 1, // TCO status
37 , 9, // skip 9 more bits
38 SCIS, 1, // TCO DMI status
39 , 6 // To the end of the word
40 }
41
42 // ICH7 GPIO IO mapped registers (0x1f.0 reg 0x48.l)
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame]43 OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x3c)
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]44 Field(GPIO, ByteAcc, NoLock, Preserve)
45 {
46 Offset(0x00), // GPIO Use Select
47 GU00, 8,
48 GU01, 8,
49 GU02, 8,
50 GU03, 8,
51 Offset(0x04), // GPIO IO Select
52 GIO0, 8,
53 GIO1, 8,
54 GIO2, 8,
55 GIO3, 8,
56 Offset(0x0c), // GPIO Level
Sven Schnelle8a539b62011-04-01 07:28:35 +0000[diff] [blame]57 GP00, 1,
58 GP01, 1,
59 GP02, 1,
60 GP03, 1,
61 GP04, 1,
62 GP05, 1,
63 GP06, 1, // GDET
64 GP07, 1,
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame]65 GP08, 1,
Sven Schnelle8a539b62011-04-01 07:28:35 +0000[diff] [blame]66 GP09, 1, // HPMU
67 GP10, 1, // GPSE
68 GP11, 1,
69 GP12, 1, // WLED
70 GP13, 1, // BLED
71 GP14, 1, // GLED
72 GP15, 1, // GDIS
73 GP16, 1,
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame]74 GP17, 1,
Sven Schnelle8a539b62011-04-01 07:28:35 +0000[diff] [blame]75 GP18, 1, // SPCI
76 GP19, 1, // TSDT
77 GP20, 1, // SCPU
78 GP21, 1,
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame]79 GP22, 1,
Sven Schnelle8a539b62011-04-01 07:28:35 +0000[diff] [blame]80 GP23, 1, // LANP
81 GP24, 1, // DKLR
82 GP25, 1, // WLAN
83 GP26, 1, // SATA_PWR_EN #0 / SPOF
84 GP27, 1, // SATA_PWR_EN #1 / SPMU
85 GP28, 1,
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame]86 GP29, 1,
87 GP30, 1,
88 GP31, 1,
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]89 Offset(0x18), // GPIO Blink
90 GB00, 8,
91 GB01, 8,
92 GB02, 8,
93 GB03, 8,
94 Offset(0x2c), // GPIO Invert
95 GIV0, 8,
96 GIV1, 8,
97 GIV2, 8,
98 GIV3, 8,
99 Offset(0x30), // GPIO Use Select 2
100 GU04, 8,
101 GU05, 8,
102 GU06, 8,
103 GU07, 8,
104 Offset(0x34), // GPIO IO Select 2
105 GIO4, 8,
106 GIO5, 8,
107 GIO6, 8,
108 GIO7, 8,
109 Offset(0x38), // GPIO Level 2
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame]110 GP32, 1,
111 GP33, 1, // CREN
112 GP34, 1, // CRRS
113 GP35, 1,
114 GP36, 1, // STAD
115 GP37, 1, // PATA_PWR_EN / HDDE
116 GP38, 1, // Battery / Power (?) / MB00
117 GP39, 1, // ?? / MB01
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]118 GL05, 8,
119 GL06, 8,
120 GL07, 8
121 }
122
123
124 // ICH7 Root Complex Register Block. Memory Mapped through RCBA)
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame]125 OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000)
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]126 Field(RCRB, DWordAcc, Lock, Preserve)
127 {
128 Offset(0x0000), // Backbone
129 Offset(0x1000), // Chipset
130 Offset(0x3000), // Legacy Configuration Registers
131 Offset(0x3404), // High Performance Timer Configuration
Elyes HAOUASb0f19882018-06-09 11:59:00 +0200[diff] [blame^]132 HPAS, 2, // Address Select
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]133 , 5,
134 HPTE, 1, // Address Enable
135 Offset(0x3418), // FD (Function Disable)
Stefan Reinauer573f7d42009-07-21 21:50:34 +0000[diff] [blame]136 , 1, // Reserved
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]137 PATD, 1, // PATA disable
138 SATD, 1, // SATA disable
139 SMBD, 1, // SMBUS disable
140 HDAD, 1, // Azalia disable
Stefan Reinauer573f7d42009-07-21 21:50:34 +0000[diff] [blame]141 A97D, 1, // AC'97 disable
142 M97D, 1, // AC'97 disable
143 ILND, 1, // Internal LAN disable
144 US1D, 1, // UHCI #1 disable
145 US2D, 1, // UHCI #2 disable
146 US3D, 1, // UHCI #3 disable
147 US4D, 1, // UHCI #4 disable
148 , 2, // Reserved
149 LPBD, 1, // LPC bridge disable
150 EHCD, 1, // EHCI disable
151 Offset(0x341a), // FD Root Ports
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]152 RP1D, 1, // Root Port 1 disable
153 RP2D, 1, // Root Port 2 disable
154 RP3D, 1, // Root Port 3 disable
155 RP4D, 1, // Root Port 4 disable
156 RP5D, 1, // Root Port 5 disable
157 RP6D, 1 // Root Port 6 disable
158 }
Stefan Reinauer109ab312009-08-12 16:08:05 +0000[diff] [blame]159
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]160}
161
162// 0:1b.0 High Definition Audio (Azalia)
Patrick Georgi334328a2012-02-16 19:01:22 +0100[diff] [blame]163#include "audio.asl"
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]164
165// PCI Express Ports
Patrick Georgi334328a2012-02-16 19:01:22 +0100[diff] [blame]166#include "pcie.asl"
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]167
168// USB
Patrick Georgi334328a2012-02-16 19:01:22 +0100[diff] [blame]169#include "usb.asl"
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]170
171// PCI Bridge
Patrick Georgi334328a2012-02-16 19:01:22 +0100[diff] [blame]172#include "pci.asl"
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]173
Stefan Reinauer573f7d42009-07-21 21:50:34 +0000[diff] [blame]174// AC97 Audio and Modem
Patrick Georgi334328a2012-02-16 19:01:22 +0100[diff] [blame]175#include "ac97.asl"
Stefan Reinauer573f7d42009-07-21 21:50:34 +0000[diff] [blame]176
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]177// LPC Bridge
Patrick Georgi334328a2012-02-16 19:01:22 +0100[diff] [blame]178#include "lpc.asl"
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]179
180// PATA
Patrick Georgi334328a2012-02-16 19:01:22 +0100[diff] [blame]181#include "pata.asl"
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]182
183// SATA
Patrick Georgi334328a2012-02-16 19:01:22 +0100[diff] [blame]184#include "sata.asl"
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]185
186// SMBus
Patrick Georgi334328a2012-02-16 19:01:22 +0100[diff] [blame]187#include "smbus.asl"