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review.coreboot.org / coreboot / 182dbdeac4b2489f8d03a47a79ab28ad556d9d21 / . / src / southbridge / intel / i82801gx / acpi / ich7.asl
blob: 191797954d102d13b14d9ff0e593d691d72d4f96 [file] [log] [blame]
Angel Pons182dbde2020-04-02 23:49:05 +0200[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0-only */
2/* This file is part of the coreboot project. */
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]3
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame]4/* Intel 82801Gx support */
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]5
Elyes HAOUAS484efff2018-12-20 08:46:02 +0100[diff] [blame]6#include "../i82801gx.h"
7
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]8Scope(\)
9{
10 // IO-Trap at 0x800. This is the ACPI->SMI communication interface.
11
12 OperationRegion(IO_T, SystemIO, 0x800, 0x10)
13 Field(IO_T, ByteAcc, NoLock, Preserve)
14 {
15 Offset(0x8),
16 TRP0, 8 // IO-Trap at 0x808
17 }
18
19 // ICH7 Power Management Registers, located at PMBASE (0x1f.0 0x40.l)
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame]20 OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80)
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]21 Field(PMIO, ByteAcc, NoLock, Preserve)
22 {
23 Offset(0x42), // General Purpose Control
24 , 1, // skip 1 bit
25 GPEC, 1, // TCO status
26 , 9, // skip 9 more bits
27 SCIS, 1, // TCO DMI status
28 , 6 // To the end of the word
29 }
30
31 // ICH7 GPIO IO mapped registers (0x1f.0 reg 0x48.l)
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame]32 OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x3c)
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]33 Field(GPIO, ByteAcc, NoLock, Preserve)
34 {
Elyes HAOUAS80505a62019-03-01 11:07:06 +0100[diff] [blame]35 // GPIO Use Select
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]36 GU00, 8,
37 GU01, 8,
38 GU02, 8,
39 GU03, 8,
Elyes HAOUAS80505a62019-03-01 11:07:06 +0100[diff] [blame]40 // GPIO IO Select
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]41 GIO0, 8,
42 GIO1, 8,
43 GIO2, 8,
44 GIO3, 8,
45 Offset(0x0c), // GPIO Level
Sven Schnelle8a539b62011-04-01 07:28:35 +0000[diff] [blame]46 GP00, 1,
47 GP01, 1,
48 GP02, 1,
49 GP03, 1,
50 GP04, 1,
51 GP05, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]52 GP06, 1,
Sven Schnelle8a539b62011-04-01 07:28:35 +0000[diff] [blame]53 GP07, 1,
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame]54 GP08, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]55 GP09, 1,
56 GP10, 1,
Sven Schnelle8a539b62011-04-01 07:28:35 +0000[diff] [blame]57 GP11, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]58 GP12, 1,
59 GP13, 1,
60 GP14, 1,
61 GP15, 1,
Sven Schnelle8a539b62011-04-01 07:28:35 +0000[diff] [blame]62 GP16, 1,
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame]63 GP17, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]64 GP18, 1,
65 GP19, 1,
66 GP20, 1,
Sven Schnelle8a539b62011-04-01 07:28:35 +0000[diff] [blame]67 GP21, 1,
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame]68 GP22, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]69 GP23, 1,
70 GP24, 1,
71 GP25, 1,
72 GP26, 1,
73 GP27, 1,
Sven Schnelle8a539b62011-04-01 07:28:35 +0000[diff] [blame]74 GP28, 1,
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame]75 GP29, 1,
76 GP30, 1,
77 GP31, 1,
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]78 Offset(0x18), // GPIO Blink
79 GB00, 8,
80 GB01, 8,
81 GB02, 8,
82 GB03, 8,
83 Offset(0x2c), // GPIO Invert
84 GIV0, 8,
85 GIV1, 8,
86 GIV2, 8,
87 GIV3, 8,
Elyes HAOUAS80505a62019-03-01 11:07:06 +0100[diff] [blame]88 // GPIO Use Select 2
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]89 GU04, 8,
90 GU05, 8,
91 GU06, 8,
92 GU07, 8,
Elyes HAOUAS80505a62019-03-01 11:07:06 +0100[diff] [blame]93 // GPIO IO Select 2
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]94 GIO4, 8,
95 GIO5, 8,
96 GIO6, 8,
97 GIO7, 8,
Elyes HAOUAS80505a62019-03-01 11:07:06 +0100[diff] [blame]98 // GPIO Level 2
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame]99 GP32, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]100 GP33, 1,
101 GP34, 1,
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame]102 GP35, 1,
Stefan Tauner1758e732018-08-04 22:03:12 +0200[diff] [blame]103 GP36, 1,
104 GP37, 1,
105 GP38, 1,
106 GP39, 1,
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]107 GL05, 8,
108 GL06, 8,
109 GL07, 8
110 }
111
112
113 // ICH7 Root Complex Register Block. Memory Mapped through RCBA)
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame]114 OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000)
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]115 Field(RCRB, DWordAcc, Lock, Preserve)
116 {
Elyes HAOUAS80505a62019-03-01 11:07:06 +0100[diff] [blame]117 // Backbone
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]118 Offset(0x1000), // Chipset
119 Offset(0x3000), // Legacy Configuration Registers
120 Offset(0x3404), // High Performance Timer Configuration
Elyes HAOUASb0f19882018-06-09 11:59:00 +0200[diff] [blame]121 HPAS, 2, // Address Select
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]122 , 5,
123 HPTE, 1, // Address Enable
124 Offset(0x3418), // FD (Function Disable)
Stefan Reinauer573f7d42009-07-21 21:50:34 +0000[diff] [blame]125 , 1, // Reserved
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]126 PATD, 1, // PATA disable
127 SATD, 1, // SATA disable
128 SMBD, 1, // SMBUS disable
129 HDAD, 1, // Azalia disable
Stefan Reinauer573f7d42009-07-21 21:50:34 +0000[diff] [blame]130 A97D, 1, // AC'97 disable
131 M97D, 1, // AC'97 disable
132 ILND, 1, // Internal LAN disable
133 US1D, 1, // UHCI #1 disable
134 US2D, 1, // UHCI #2 disable
135 US3D, 1, // UHCI #3 disable
136 US4D, 1, // UHCI #4 disable
137 , 2, // Reserved
138 LPBD, 1, // LPC bridge disable
139 EHCD, 1, // EHCI disable
Elyes HAOUAS80505a62019-03-01 11:07:06 +0100[diff] [blame]140 // FD Root Ports
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]141 RP1D, 1, // Root Port 1 disable
142 RP2D, 1, // Root Port 2 disable
143 RP3D, 1, // Root Port 3 disable
144 RP4D, 1, // Root Port 4 disable
145 RP5D, 1, // Root Port 5 disable
146 RP6D, 1 // Root Port 6 disable
147 }
Stefan Reinauer109ab312009-08-12 16:08:05 +0000[diff] [blame]148
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]149}
150
151// 0:1b.0 High Definition Audio (Azalia)
Patrick Georgi334328a2012-02-16 19:01:22 +0100[diff] [blame]152#include "audio.asl"
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]153
154// PCI Express Ports
Arthur Heymansdff185a2018-12-30 12:59:39 +0100[diff] [blame]155#include <southbridge/intel/common/acpi/pcie.asl>
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]156
157// USB
Patrick Georgi334328a2012-02-16 19:01:22 +0100[diff] [blame]158#include "usb.asl"
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]159
160// PCI Bridge
Patrick Georgi334328a2012-02-16 19:01:22 +0100[diff] [blame]161#include "pci.asl"
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]162
Stefan Reinauer573f7d42009-07-21 21:50:34 +0000[diff] [blame]163// AC97 Audio and Modem
Patrick Georgi334328a2012-02-16 19:01:22 +0100[diff] [blame]164#include "ac97.asl"
Stefan Reinauer573f7d42009-07-21 21:50:34 +0000[diff] [blame]165
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]166// LPC Bridge
Patrick Georgi334328a2012-02-16 19:01:22 +0100[diff] [blame]167#include "lpc.asl"
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]168
169// PATA
Patrick Georgi334328a2012-02-16 19:01:22 +0100[diff] [blame]170#include "pata.asl"
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]171
172// SATA
Patrick Georgi334328a2012-02-16 19:01:22 +0100[diff] [blame]173#include "sata.asl"
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]174
175// SMBus
Elyes HAOUAS085ab5a2019-10-31 10:12:02 +0100[diff] [blame]176#include <southbridge/intel/common/acpi/smbus.asl>