Gitiles
Code Review Sign In
review.coreboot.org / coreboot / aca6ec66bf7048e77ec960bb751a04e6b0528c70 / . / src / southbridge / intel / i82801gx / acpi / ich7.asl
blob: a37208c021e9d46e9c168425616ba977b14c01be [file] [log] [blame]
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
19 * MA 02110-1301 USA
20 */
21
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame^]22/* Intel 82801Gx support */
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]23
24Scope(\)
25{
26 // IO-Trap at 0x800. This is the ACPI->SMI communication interface.
27
28 OperationRegion(IO_T, SystemIO, 0x800, 0x10)
29 Field(IO_T, ByteAcc, NoLock, Preserve)
30 {
31 Offset(0x8),
32 TRP0, 8 // IO-Trap at 0x808
33 }
34
35 // ICH7 Power Management Registers, located at PMBASE (0x1f.0 0x40.l)
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame^]36 OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80)
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]37 Field(PMIO, ByteAcc, NoLock, Preserve)
38 {
39 Offset(0x42), // General Purpose Control
40 , 1, // skip 1 bit
41 GPEC, 1, // TCO status
42 , 9, // skip 9 more bits
43 SCIS, 1, // TCO DMI status
44 , 6 // To the end of the word
45 }
46
47 // ICH7 GPIO IO mapped registers (0x1f.0 reg 0x48.l)
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame^]48 OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x3c)
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]49 Field(GPIO, ByteAcc, NoLock, Preserve)
50 {
51 Offset(0x00), // GPIO Use Select
52 GU00, 8,
53 GU01, 8,
54 GU02, 8,
55 GU03, 8,
56 Offset(0x04), // GPIO IO Select
57 GIO0, 8,
58 GIO1, 8,
59 GIO2, 8,
60 GIO3, 8,
61 Offset(0x0c), // GPIO Level
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame^]62 GL00, 6,
63 GP07, 1, // GDET
64 GP08, 1,
65 GP09, 1,
66 GP10, 1, // HPMU
67 GP11, 1, // GPSE
68 GP12, 1,
69 GP13, 1, // WLED
70 GP14, 1, // BLED
71 GP15, 1, // GLED
72 GP16, 1, // GDIS
73 GP17, 1,
74 GP18, 1,
75 GP19, 1, // SPCI
76 GP20, 1, // TSDT
77 GP21, 1, // SCPU
78 GP22, 1,
79 GP23, 1,
80 GP24, 1, // LANP
81 GP25, 1, // DKLR
82 GP26, 1, // WLAN
83 GP27, 1, // SATA_PWR_EN #0 / SPOF
84 GP28, 1, // SATA_PWR_EN #1 / SPMU
85 GP29, 1,
86 GP30, 1,
87 GP31, 1,
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]88 Offset(0x18), // GPIO Blink
89 GB00, 8,
90 GB01, 8,
91 GB02, 8,
92 GB03, 8,
93 Offset(0x2c), // GPIO Invert
94 GIV0, 8,
95 GIV1, 8,
96 GIV2, 8,
97 GIV3, 8,
98 Offset(0x30), // GPIO Use Select 2
99 GU04, 8,
100 GU05, 8,
101 GU06, 8,
102 GU07, 8,
103 Offset(0x34), // GPIO IO Select 2
104 GIO4, 8,
105 GIO5, 8,
106 GIO6, 8,
107 GIO7, 8,
108 Offset(0x38), // GPIO Level 2
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame^]109 GP32, 1,
110 GP33, 1, // CREN
111 GP34, 1, // CRRS
112 GP35, 1,
113 GP36, 1, // STAD
114 GP37, 1, // PATA_PWR_EN / HDDE
115 GP38, 1, // Battery / Power (?) / MB00
116 GP39, 1, // ?? / MB01
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]117 GL05, 8,
118 GL06, 8,
119 GL07, 8
120 }
121
122
123 // ICH7 Root Complex Register Block. Memory Mapped through RCBA)
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame^]124 OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000)
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]125 Field(RCRB, DWordAcc, Lock, Preserve)
126 {
127 Offset(0x0000), // Backbone
128 Offset(0x1000), // Chipset
129 Offset(0x3000), // Legacy Configuration Registers
130 Offset(0x3404), // High Performance Timer Configuration
Stefan Reinauer109ab312009-08-12 16:08:05 +0000[diff] [blame]131 HPAS, 2, // Address Select
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]132 , 5,
133 HPTE, 1, // Address Enable
134 Offset(0x3418), // FD (Function Disable)
Stefan Reinauer573f7d42009-07-21 21:50:34 +0000[diff] [blame]135 , 1, // Reserved
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]136 PATD, 1, // PATA disable
137 SATD, 1, // SATA disable
138 SMBD, 1, // SMBUS disable
139 HDAD, 1, // Azalia disable
Stefan Reinauer573f7d42009-07-21 21:50:34 +0000[diff] [blame]140 A97D, 1, // AC'97 disable
141 M97D, 1, // AC'97 disable
142 ILND, 1, // Internal LAN disable
143 US1D, 1, // UHCI #1 disable
144 US2D, 1, // UHCI #2 disable
145 US3D, 1, // UHCI #3 disable
146 US4D, 1, // UHCI #4 disable
147 , 2, // Reserved
148 LPBD, 1, // LPC bridge disable
149 EHCD, 1, // EHCI disable
150 Offset(0x341a), // FD Root Ports
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]151 RP1D, 1, // Root Port 1 disable
152 RP2D, 1, // Root Port 2 disable
153 RP3D, 1, // Root Port 3 disable
154 RP4D, 1, // Root Port 4 disable
155 RP5D, 1, // Root Port 5 disable
156 RP6D, 1 // Root Port 6 disable
157 }
Stefan Reinauer109ab312009-08-12 16:08:05 +0000[diff] [blame]158
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]159}
160
161// 0:1b.0 High Definition Audio (Azalia)
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame^]162#include "../../../southbridge/intel/i82801gx/acpi/ich7_audio.asl"
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]163
164// PCI Express Ports
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame^]165#include "../../../southbridge/intel/i82801gx/acpi/ich7_pcie.asl"
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]166
167// USB
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame^]168#include "../../../southbridge/intel/i82801gx/acpi/ich7_usb.asl"
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]169
170// PCI Bridge
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame^]171#include "../../../southbridge/intel/i82801gx/acpi/ich7_pci.asl"
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]172
Stefan Reinauer573f7d42009-07-21 21:50:34 +0000[diff] [blame]173// AC97 Audio and Modem
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame^]174#include "../../../southbridge/intel/i82801gx/acpi/ich7_ac97.asl"
Stefan Reinauer573f7d42009-07-21 21:50:34 +0000[diff] [blame]175
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]176// LPC Bridge
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame^]177#include "../../../southbridge/intel/i82801gx/acpi/ich7_lpc.asl"
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]178
179// PATA
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame^]180#include "../../../southbridge/intel/i82801gx/acpi/ich7_pata.asl"
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]181
182// SATA
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame^]183#include "../../../southbridge/intel/i82801gx/acpi/ich7_sata.asl"
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]184
185// SMBus
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame^]186#include "../../../southbridge/intel/i82801gx/acpi/ich7_smbus.asl"
Stefan Reinauercc46e732009-03-13 00:44:09 +0000[diff] [blame]187
188