sb/intel/i82801gx: Remove unnecessary/redundant ACPI offset operator
Using ACPICA version 20180927 or greater, IASL detects Unnecessary/redundant
uses of the Offset() operator within a Field Unit list.
It then sends a remark "^ Unnecessary/redundant use of Offset".
Offsets refer to the current offset are unnecessary.
example:
OperationRegion (OPR1, SystemMemory, 0x100, 0x100)
Field (OPR1)
{
Offset (0), // Never needed
FLD1, 32,
Offset (4), // Redundant, offset is already 4 (bytes)
FLD2, 8,
Offset (64), // OK use of Offset.
FLD3, 16,
}
We will have those remarks:
dsdt.asl 14: Offset (0),
Remark 2158 - ^ Unnecessary/redundant use of Offset
operator
dsdt.asl 16: Offset (4),
Remark 2158 - ^ Unnecessary/redundant use of Offset
operator
Change-Id: If53072c6a91dd794c70d1fab8697b1713d400fe8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7.asl b/src/southbridge/intel/i82801gx/acpi/ich7.asl
index 38ca483..d24c8af 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7.asl
+++ b/src/southbridge/intel/i82801gx/acpi/ich7.asl
@@ -43,12 +43,12 @@
OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x3c)
Field(GPIO, ByteAcc, NoLock, Preserve)
{
- Offset(0x00), // GPIO Use Select
+ // GPIO Use Select
GU00, 8,
GU01, 8,
GU02, 8,
GU03, 8,
- Offset(0x04), // GPIO IO Select
+ // GPIO IO Select
GIO0, 8,
GIO1, 8,
GIO2, 8,
@@ -96,17 +96,17 @@
GIV1, 8,
GIV2, 8,
GIV3, 8,
- Offset(0x30), // GPIO Use Select 2
+ // GPIO Use Select 2
GU04, 8,
GU05, 8,
GU06, 8,
GU07, 8,
- Offset(0x34), // GPIO IO Select 2
+ // GPIO IO Select 2
GIO4, 8,
GIO5, 8,
GIO6, 8,
GIO7, 8,
- Offset(0x38), // GPIO Level 2
+ // GPIO Level 2
GP32, 1,
GP33, 1,
GP34, 1,
@@ -125,7 +125,7 @@
OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000)
Field(RCRB, DWordAcc, Lock, Preserve)
{
- Offset(0x0000), // Backbone
+ // Backbone
Offset(0x1000), // Chipset
Offset(0x3000), // Legacy Configuration Registers
Offset(0x3404), // High Performance Timer Configuration
@@ -148,7 +148,7 @@
, 2, // Reserved
LPBD, 1, // LPC bridge disable
EHCD, 1, // EHCI disable
- Offset(0x341a), // FD Root Ports
+ // FD Root Ports
RP1D, 1, // Root Port 1 disable
RP2D, 1, // Root Port 2 disable
RP3D, 1, // Root Port 3 disable