Wonkyu Kim | 7e30358 | 2020-03-06 14:36:23 -0800 | [diff] [blame] | 1 | chip soc/intel/tigerlake |
| 2 | |
| 3 | device cpu_cluster 0 on |
| 4 | device lapic 0 on end |
| 5 | end |
| 6 | |
Shaunak Saha | d72cca0 | 2020-03-25 11:42:12 -0700 | [diff] [blame] | 7 | # GPE configuration |
| 8 | # Note that GPE events called out in ASL code rely on this |
| 9 | # route. i.e. If this route changes then the affected GPE |
| 10 | # offset bits also need to be changed. |
| 11 | register "pmc_gpe0_dw0" = "GPP_B" |
Shaunak Saha | b449b9c | 2020-08-23 21:35:21 -0700 | [diff] [blame^] | 12 | register "pmc_gpe0_dw1" = "GPP_C" |
| 13 | register "pmc_gpe0_dw2" = "GPP_D" |
Shaunak Saha | d72cca0 | 2020-03-25 11:42:12 -0700 | [diff] [blame] | 14 | |
Jamie Ryu | 5a401ae | 2020-06-12 02:47:14 -0700 | [diff] [blame] | 15 | # Enable heci1 communication |
| 16 | register "HeciEnabled" = "1" |
| 17 | |
Wonkyu Kim | 7e30358 | 2020-03-06 14:36:23 -0800 | [diff] [blame] | 18 | # FSP configuration |
| 19 | register "SaGv" = "SaGv_Disabled" |
| 20 | register "SmbusEnable" = "1" |
| 21 | |
| 22 | register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1 |
| 23 | register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN |
Jason Le | 2b34161 | 2020-08-27 15:16:32 -0700 | [diff] [blame] | 24 | register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # M.2 Bluetooth, USB3/2 Type A Port1 |
| 25 | register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A Port 1 |
Wonkyu Kim | 7e30358 | 2020-03-06 14:36:23 -0800 | [diff] [blame] | 26 | register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port2 |
Jason Le | 2b34161 | 2020-08-27 15:16:32 -0700 | [diff] [blame] | 27 | register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 / MECC |
| 28 | register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Not used |
| 29 | register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Not used |
| 30 | register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Not used |
Wonkyu Kim | 7e30358 | 2020-03-06 14:36:23 -0800 | [diff] [blame] | 31 | register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # CNVi/BT |
| 32 | |
| 33 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1 |
| 34 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 |
Wonkyu Kim | 7e30358 | 2020-03-06 14:36:23 -0800 | [diff] [blame] | 35 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # USB3/USB2 Flex Connector |
| 36 | |
Angel Pons | e16692e | 2020-08-03 12:54:48 +0200 | [diff] [blame] | 37 | # CPU replacement check |
| 38 | register "CpuReplacementCheck" = "1" |
Jamie Ryu | ef079c8 | 2020-06-24 15:55:10 -0700 | [diff] [blame] | 39 | |
Wonkyu Kim | 7e30358 | 2020-03-06 14:36:23 -0800 | [diff] [blame] | 40 | # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| 41 | register "gen1_dec" = "0x00fc0801" |
| 42 | register "gen2_dec" = "0x000c0201" |
| 43 | # EC memory map range is 0x900-0x9ff |
| 44 | register "gen3_dec" = "0x00fc0901" |
| 45 | |
Wonkyu Kim | 7e30358 | 2020-03-06 14:36:23 -0800 | [diff] [blame] | 46 | register "PcieRpEnable[2]" = "1" |
| 47 | register "PcieRpEnable[3]" = "1" |
| 48 | register "PcieRpEnable[8]" = "1" |
| 49 | register "PcieRpEnable[10]" = "1" |
| 50 | |
Wonkyu Kim | 53ac68e | 2020-04-07 23:37:11 -0700 | [diff] [blame] | 51 | # Enable PR LTR |
| 52 | register "PcieRpLtrEnable[2]" = "1" |
| 53 | register "PcieRpLtrEnable[3]" = "1" |
| 54 | register "PcieRpLtrEnable[8]" = "1" |
| 55 | register "PcieRpLtrEnable[10]" = "1" |
| 56 | |
Wonkyu Kim | f787e87 | 2020-03-03 01:58:17 -0800 | [diff] [blame] | 57 | # Hybrid storage mode |
| 58 | register "HybridStorageMode" = "1" |
| 59 | |
Wonkyu Kim | 7e30358 | 2020-03-06 14:36:23 -0800 | [diff] [blame] | 60 | register "PcieClkSrcClkReq[1]" = "1" |
| 61 | register "PcieClkSrcClkReq[2]" = "2" |
| 62 | register "PcieClkSrcClkReq[3]" = "3" |
| 63 | |
| 64 | register "PcieClkSrcUsage[1]" = "0x2" |
| 65 | register "PcieClkSrcUsage[2]" = "0x3" |
| 66 | register "PcieClkSrcUsage[3]" = "0x8" |
| 67 | |
| 68 | # enabling EDP in PortA |
| 69 | register "DdiPortAConfig" = "1" |
| 70 | |
Jason Le | 2b34161 | 2020-08-27 15:16:32 -0700 | [diff] [blame] | 71 | register "DdiPortAHpd" = "1" |
| 72 | register "DdiPortADdc" = "0" |
Wonkyu Kim | 6681511 | 2020-03-09 14:48:51 -0700 | [diff] [blame] | 73 | register "DdiPortBHpd" = "1" |
Jason Le | 2b34161 | 2020-08-27 15:16:32 -0700 | [diff] [blame] | 74 | register "DdiPortBDdc" = "1" |
| 75 | register "DdiPortCHpd" = "0" |
| 76 | register "DdiPortCDdc" = "0" |
Wonkyu Kim | 7e30358 | 2020-03-06 14:36:23 -0800 | [diff] [blame] | 77 | register "DdiPort1Hpd" = "1" |
Jason Le | 2b34161 | 2020-08-27 15:16:32 -0700 | [diff] [blame] | 78 | register "DdiPort1Ddc" = "0" |
| 79 | register "DdiPort2Hpd" = "1" |
| 80 | register "DdiPort2Ddc" = "0" |
Wonkyu Kim | 7e30358 | 2020-03-06 14:36:23 -0800 | [diff] [blame] | 81 | |
| 82 | register "SerialIoI2cMode" = "{ |
| 83 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 84 | [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| 85 | [PchSerialIoIndexI2C2] = PchSerialIoPci, |
| 86 | [PchSerialIoIndexI2C3] = PchSerialIoPci, |
| 87 | [PchSerialIoIndexI2C4] = PchSerialIoDisabled, |
| 88 | [PchSerialIoIndexI2C5] = PchSerialIoPci, |
| 89 | }" |
| 90 | |
| 91 | register "SerialIoGSpiMode" = "{ |
| 92 | [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, |
Shaunak Saha | b449b9c | 2020-08-23 21:35:21 -0700 | [diff] [blame^] | 93 | [PchSerialIoIndexGSPI1] = PchSerialIoPci, |
Wonkyu Kim | 7e30358 | 2020-03-06 14:36:23 -0800 | [diff] [blame] | 94 | [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, |
| 95 | [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, |
| 96 | }" |
| 97 | |
| 98 | register "SerialIoGSpiCsMode" = "{ |
| 99 | [PchSerialIoIndexGSPI0] = 0, |
Shaunak Saha | b449b9c | 2020-08-23 21:35:21 -0700 | [diff] [blame^] | 100 | [PchSerialIoIndexGSPI1] = 1, |
Wonkyu Kim | 7e30358 | 2020-03-06 14:36:23 -0800 | [diff] [blame] | 101 | [PchSerialIoIndexGSPI2] = 0, |
| 102 | [PchSerialIoIndexGSPI3] = 0, |
| 103 | }" |
| 104 | |
| 105 | register "SerialIoGSpiCsState" = "{ |
| 106 | [PchSerialIoIndexGSPI0] = 0, |
| 107 | [PchSerialIoIndexGSPI1] = 0, |
| 108 | [PchSerialIoIndexGSPI2] = 0, |
| 109 | [PchSerialIoIndexGSPI3] = 0, |
| 110 | }" |
| 111 | |
| 112 | register "SerialIoUartMode" = "{ |
| 113 | [PchSerialIoIndexUART0] = PchSerialIoDisabled, |
| 114 | [PchSerialIoIndexUART1] = PchSerialIoDisabled, |
| 115 | [PchSerialIoIndexUART2] = PchSerialIoPci, |
| 116 | }" |
| 117 | |
John Zhao | b1c53fc | 2020-05-13 16:27:03 -0700 | [diff] [blame] | 118 | # TCSS USB3 |
| 119 | register "TcssXhciEn" = "1" |
| 120 | register "TcssAuxOri" = "0" |
| 121 | |
Shreesh Chhabbi | ca128a0 | 2020-08-27 16:41:42 -0700 | [diff] [blame] | 122 | # Enable "Intel Speed Shift Technology" |
| 123 | register "speed_shift_enable" = "1" |
| 124 | |
John Zhao | 23d3ad0 | 2020-06-30 17:36:24 -0700 | [diff] [blame] | 125 | # Enable S0ix |
| 126 | register "s0ix_enable" = "1" |
| 127 | |
Sumeet R Pawnikar | 06b35e5 | 2020-09-09 23:44:06 +0530 | [diff] [blame] | 128 | # Enable DPTF |
| 129 | register "dptf_enable" = "1" |
| 130 | |
| 131 | # Enable Processor Thermal Control |
| 132 | register "Device4Enable" = "1" |
| 133 | |
| 134 | # Add PL1 and PL2 values |
| 135 | register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ |
| 136 | .tdp_pl1_override = 9, |
| 137 | .tdp_pl2_override = 35, |
| 138 | .tdp_pl4 = 66, |
| 139 | }" |
| 140 | register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ |
| 141 | .tdp_pl1_override = 9, |
| 142 | .tdp_pl2_override = 40, |
| 143 | .tdp_pl4 = 83, |
| 144 | }" |
| 145 | |
Wonkyu Kim | 7e30358 | 2020-03-06 14:36:23 -0800 | [diff] [blame] | 146 | #HD Audio |
| 147 | register "PchHdaDspEnable" = "1" |
| 148 | register "PchHdaAudioLinkHdaEnable" = "0" |
| 149 | register "PchHdaAudioLinkDmicEnable[0]" = "1" |
| 150 | register "PchHdaAudioLinkDmicEnable[1]" = "1" |
| 151 | register "PchHdaAudioLinkSspEnable[0]" = "1" |
Srinidhi N Kaushik | 6975e07 | 2020-03-12 01:22:01 -0700 | [diff] [blame] | 152 | register "PchHdaAudioLinkSspEnable[1]" = "0" |
| 153 | register "PchHdaAudioLinkSspEnable[2]" = "1" |
| 154 | register "PchHdaAudioLinkSndwEnable[0]" = "1" |
Wonkyu Kim | 7e30358 | 2020-03-06 14:36:23 -0800 | [diff] [blame] | 155 | |
Wonkyu Kim | 5c27182 | 2020-04-03 00:42:22 -0700 | [diff] [blame] | 156 | # Intel Common SoC Config |
| 157 | register "common_soc_config" = "{ |
| 158 | .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, |
Shaunak Saha | b449b9c | 2020-08-23 21:35:21 -0700 | [diff] [blame^] | 159 | .gspi[1] = { |
| 160 | .speed_mhz = 1, |
| 161 | .early_init = 1, |
| 162 | }, |
Wonkyu Kim | 5c27182 | 2020-04-03 00:42:22 -0700 | [diff] [blame] | 163 | .i2c[0] = { |
| 164 | .speed = I2C_SPEED_FAST, |
| 165 | }, |
| 166 | .i2c[1] = { |
| 167 | .speed = I2C_SPEED_FAST, |
| 168 | }, |
| 169 | .i2c[2] = { |
| 170 | .speed = I2C_SPEED_FAST, |
| 171 | }, |
| 172 | .i2c[3] = { |
| 173 | .speed = I2C_SPEED_FAST, |
| 174 | }, |
| 175 | .i2c[5] = { |
| 176 | .speed = I2C_SPEED_FAST, |
| 177 | }, |
| 178 | }" |
| 179 | |
Wonkyu Kim | 7e30358 | 2020-03-06 14:36:23 -0800 | [diff] [blame] | 180 | device domain 0 on |
| 181 | #From EDS(575683) |
| 182 | device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y |
| 183 | device pci 02.0 on end # Graphics |
Sumeet R Pawnikar | 06b35e5 | 2020-09-09 23:44:06 +0530 | [diff] [blame] | 184 | device pci 04.0 on |
| 185 | # Default DPTF Policy for all tglrvp_up4 boards if not overridden |
| 186 | chip drivers/intel/dptf |
| 187 | register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 1000)" |
| 188 | register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" |
| 189 | |
| 190 | # Power Limits Control |
| 191 | register "controls.power_limits.pl1" = "{ |
| 192 | .min_power = 3000, |
| 193 | .max_power = 9000, |
| 194 | .time_window_min = 28 * MSECS_PER_SEC, |
| 195 | .time_window_max = 32 * MSECS_PER_SEC, |
| 196 | .granularity = 200,}" |
| 197 | register "controls.power_limits.pl2" = "{ |
| 198 | .min_power = 9000, |
| 199 | .max_power = 40000, |
| 200 | .time_window_min = 28 * MSECS_PER_SEC, |
| 201 | .time_window_max = 32 * MSECS_PER_SEC, |
| 202 | .granularity = 1000,}" |
| 203 | device generic 0 on end |
| 204 | end |
| 205 | end # DPTF 0x9A02:Y22/0x9A12:Y42 |
| 206 | |
Wonkyu Kim | 7e30358 | 2020-03-06 14:36:23 -0800 | [diff] [blame] | 207 | device pci 05.0 on end # IPU 0x9A19 |
| 208 | device pci 06.0 on end # PEG60 0x9A09 |
John Zhao | b1c53fc | 2020-05-13 16:27:03 -0700 | [diff] [blame] | 209 | device pci 07.0 on end # TBT_PCIe0 0x9A23 |
| 210 | device pci 07.1 on end # TBT_PCIe1 0x9A25 |
| 211 | device pci 07.2 on end # TBT_PCIe2 0x9A27 |
John Zhao | 3af09bb | 2020-08-18 22:32:47 -0700 | [diff] [blame] | 212 | device pci 07.3 off end # TBT_PCIe3 0x9A29 |
Wonkyu Kim | 7e30358 | 2020-03-06 14:36:23 -0800 | [diff] [blame] | 213 | device pci 08.0 off end # GNA 0x9A11 |
| 214 | device pci 09.0 off end # NPK 0x9A33 |
| 215 | device pci 0a.0 off end # Crash-log SRAM 0x9A0D |
| 216 | device pci 0d.0 on end # USB xHCI 0x9A13 |
| 217 | device pci 0d.1 on end # USB xDCI (OTG) 0x9A15 |
John Zhao | b1c53fc | 2020-05-13 16:27:03 -0700 | [diff] [blame] | 218 | device pci 0d.2 on end # TBT DMA0 0x9A1B |
| 219 | device pci 0d.3 on end # TBT DMA1 0x9A1D |
Wonkyu Kim | 165efa1 | 2020-05-05 09:10:13 -0700 | [diff] [blame] | 220 | device pci 0e.0 off end # VMD 0x9A0B |
Wonkyu Kim | 7e30358 | 2020-03-06 14:36:23 -0800 | [diff] [blame] | 221 | |
| 222 | # From PCH EDS(576591) |
| 223 | device pci 10.2 off end # CNVi: BT 0xA0F5 - A0F7 |
| 224 | device pci 10.6 off end # THC0 0xA0D0 |
| 225 | device pci 10.7 off end # THC1 0xA0D1 |
li feng | 2395425 | 2020-03-12 16:38:34 -0700 | [diff] [blame] | 226 | device pci 12.0 on # SensorHUB 0xA0FC |
| 227 | chip drivers/intel/ish |
| 228 | register "firmware_name" = ""tglrvp_ish.bin"" |
| 229 | device generic 0 on end |
| 230 | end |
| 231 | end |
Wonkyu Kim | 7e30358 | 2020-03-06 14:36:23 -0800 | [diff] [blame] | 232 | device pci 12.6 off end # GSPI2 0x34FB |
| 233 | device pci 13.0 off end # GSPI3 0xA0FD |
Elyes HAOUAS | fd8de18 | 2020-03-31 21:42:02 +0200 | [diff] [blame] | 234 | device pci 14.0 on end # USB3.1 xHCI 0xA0ED |
Wonkyu Kim | 7e30358 | 2020-03-06 14:36:23 -0800 | [diff] [blame] | 235 | device pci 14.1 on end # USB3.1 xDCI 0xA0EE |
| 236 | device pci 14.2 on end # Shared RAM 0xA0EF |
Srinidhi N Kaushik | dcd3d07 | 2020-03-05 00:41:14 -0800 | [diff] [blame] | 237 | chip drivers/intel/wifi |
| 238 | register "wake" = "GPE0_PME_B0" |
| 239 | device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 |
| 240 | end |
| 241 | |
Elyes HAOUAS | fd8de18 | 2020-03-31 21:42:02 +0200 | [diff] [blame] | 242 | device pci 15.0 on # I2C0 0xA0E8 |
Shaunak Saha | 48b388f | 2020-05-27 22:48:57 -0700 | [diff] [blame] | 243 | chip drivers/i2c/generic |
| 244 | register "hid" = ""10EC1308"" |
| 245 | register "name" = ""RTAM"" |
| 246 | register "desc" = ""Realtek RT1308 Codec"" |
| 247 | device i2c 10 on end |
| 248 | end |
Wonkyu Kim | 7e30358 | 2020-03-06 14:36:23 -0800 | [diff] [blame] | 249 | chip drivers/i2c/max98373 |
| 250 | register "vmon_slot_no" = "4" |
| 251 | register "imon_slot_no" = "5" |
| 252 | register "uid" = "0" |
| 253 | register "desc" = ""RIGHT SPEAKER AMP"" |
| 254 | register "name" = ""MAXR"" |
| 255 | device i2c 31 on end |
| 256 | end |
| 257 | chip drivers/i2c/max98373 |
| 258 | register "vmon_slot_no" = "6" |
| 259 | register "imon_slot_no" = "7" |
| 260 | register "uid" = "1" |
| 261 | register "desc" = ""LEFT SPEAKER AMP"" |
| 262 | register "name" = ""MAXL"" |
| 263 | device i2c 32 on end |
| 264 | end |
| 265 | chip drivers/i2c/generic |
| 266 | register "hid" = ""10EC5682"" |
| 267 | register "name" = ""RT58"" |
| 268 | register "desc" = ""Realtek RT5682"" |
| 269 | register "irq" = "ACPI_IRQ_EDGE_HIGH(GPP_C12_IRQ)" |
| 270 | register "probed" = "1" |
| 271 | # Set the jd_src to RT5668_JD1 for jack detection |
| 272 | register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" |
| 273 | register "property_list[0].name" = ""realtek,jd-src"" |
| 274 | register "property_list[0].integer" = "1" |
| 275 | device i2c 1a on end |
| 276 | end |
| 277 | end # I2C0 |
| 278 | device pci 15.1 on end # I2C1 0xA0E9 |
| 279 | device pci 15.2 on end # I2C2 0xA0EA |
| 280 | device pci 15.3 on end # I2C3 0xA0EB |
| 281 | device pci 16.0 on end # HECI1 0xA0E0 |
| 282 | device pci 16.1 off end # HECI2 0xA0E1 |
| 283 | device pci 16.2 off end # CSME 0xA0E2 |
| 284 | device pci 16.3 off end # CSME 0xA0E3 |
| 285 | device pci 16.4 off end # HECI3 0xA0E4 |
| 286 | device pci 16.5 off end # HECI4 0xA0E5 |
| 287 | device pci 17.0 on end # SATA 0xA0D3 |
| 288 | device pci 19.0 off end # I2C4 0xA0C5 |
| 289 | device pci 19.1 on end # I2C5 0xA0C6 |
| 290 | device pci 19.2 on end # UART2 0xA0C7 |
| 291 | device pci 1c.0 off end # RP1 0xA0B8 |
| 292 | device pci 1c.1 off end # RP2 0xA0B9 |
| 293 | device pci 1c.2 on end # RP3 0xA0BA |
| 294 | device pci 1c.3 on end # RP4 0xA0BB |
| 295 | device pci 1c.4 off end # RP5 0xA0BC |
| 296 | device pci 1c.5 off end # RP6 0xA0BD |
| 297 | device pci 1c.6 off end # RP7 0xA0BE |
| 298 | device pci 1c.7 off end # RP8 0xA0BF |
| 299 | device pci 1d.0 on end # RP9 0xA0B0 |
| 300 | device pci 1d.1 off end # RP10 0xA0B1 |
| 301 | device pci 1d.2 on end # RP11 0xA0B2 |
| 302 | device pci 1d.3 off end # RP12 0xA0B3 |
| 303 | device pci 1e.0 off end # UART0 0xA0A8 |
| 304 | device pci 1e.1 off end # UART1 0xA0A9 |
Shaunak Saha | b449b9c | 2020-08-23 21:35:21 -0700 | [diff] [blame^] | 305 | device pci 1e.2 on end # GSPI0 0xA0AA |
| 306 | device pci 1e.3 on |
| 307 | chip drivers/spi/acpi |
| 308 | register "hid" = "ACPI_DT_NAMESPACE_HID" |
| 309 | register "compat_string" = ""google,cr50"" |
| 310 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C22_IRQ)" |
| 311 | device spi 0 on end |
| 312 | end |
| 313 | end # GSPI1 0xA0AB |
John Zhao | d05b15e | 2020-07-25 17:23:53 -0700 | [diff] [blame] | 314 | device pci 1f.0 on |
| 315 | chip ec/google/chromeec |
| 316 | device pnp 0c09.0 on end |
| 317 | end |
| 318 | end # eSPI 0xA080 - A09F |
Wonkyu Kim | 7e30358 | 2020-03-06 14:36:23 -0800 | [diff] [blame] | 319 | device pci 1f.1 on end # P2SB 0xA0A0 |
John Zhao | 8466ac0 | 2020-07-13 09:29:33 -0700 | [diff] [blame] | 320 | device pci 1f.2 hidden # PMC 0xA0A1 |
| 321 | # The pmc_mux chip driver is a placeholder for the |
| 322 | # PMC.MUX device in the ACPI hierarchy. |
| 323 | chip drivers/intel/pmc_mux |
| 324 | device generic 0 on |
| 325 | chip drivers/intel/pmc_mux/conn |
| 326 | register "usb2_port_number" = "6" |
| 327 | register "usb3_port_number" = "3" |
| 328 | # SBU is fixed, HSL follows CC |
| 329 | register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" |
| 330 | device generic 0 on end |
| 331 | end |
| 332 | chip drivers/intel/pmc_mux/conn |
| 333 | register "usb2_port_number" = "5" |
| 334 | register "usb3_port_number" = "2" |
| 335 | # SBU is fixed, HSL follows CC |
| 336 | register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" |
| 337 | device generic 1 on end |
| 338 | end |
| 339 | end |
| 340 | end |
| 341 | end # PMC |
Wonkyu Kim | 7e30358 | 2020-03-06 14:36:23 -0800 | [diff] [blame] | 342 | device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF |
| 343 | device pci 1f.4 on end # SMBus 0xA0A3 |
| 344 | device pci 1f.5 on end # SPI 0xA0A4 |
| 345 | device pci 1f.6 off end # GbE 0x15E1/0x15E2 |
| 346 | device pci 1f.7 off end # TH 0xA0A6 |
| 347 | end |
| 348 | end |