mb/intel/tglrvp: Add TGL UP4 RVP
Add initial TGL UP4 RVP build enviorment
BUG=none
BRANCH=none
TEST= Build TGL UP4 successfully
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Iab7ada0746394539586e7cc159112dc8208fdd7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39363
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
new file mode 100644
index 0000000..a937ab3
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -0,0 +1,203 @@
+chip soc/intel/tigerlake
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+
+ # FSP configuration
+ register "SaGv" = "SaGv_Disabled"
+ register "SmbusEnable" = "1"
+
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # M.2 Bluetooth, USB3/2 Type A port1
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port1
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port2
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3
+ register "usb3_ports[6]" = "USB3_PORT_EMPTY" # Not used
+ register "usb3_ports[7]" = "USB3_PORT_EMPTY" # Not used
+ register "usb3_ports[8]" = "USB3_PORT_EMPTY" # Not used
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # CNVi/BT
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2
+ register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Not used
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # USB3/USB2 Flex Connector
+
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
+ # EC memory map range is 0x900-0x9ff
+ register "gen3_dec" = "0x00fc0901"
+
+ register "PrmrrSize" = "0x10000000"
+
+ register "PcieRpEnable[2]" = "1"
+ register "PcieRpEnable[3]" = "1"
+ register "PcieRpEnable[8]" = "1"
+ register "PcieRpEnable[10]" = "1"
+
+ register "PcieClkSrcClkReq[1]" = "1"
+ register "PcieClkSrcClkReq[2]" = "2"
+ register "PcieClkSrcClkReq[3]" = "3"
+
+ register "PcieClkSrcUsage[1]" = "0x2"
+ register "PcieClkSrcUsage[2]" = "0x3"
+ register "PcieClkSrcUsage[3]" = "0x8"
+
+ # enabling EDP in PortA
+ register "DdiPortAConfig" = "1"
+
+ register "DdiPort1Hpd" = "1"
+ register "DdiPort1Ddc" = "1"
+
+ register "SerialIoI2cMode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C1] = PchSerialIoPci,
+ [PchSerialIoIndexI2C2] = PchSerialIoPci,
+ [PchSerialIoIndexI2C3] = PchSerialIoPci,
+ [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C5] = PchSerialIoPci,
+ }"
+
+ register "SerialIoGSpiMode" = "{
+ [PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
+ [PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
+ [PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
+ [PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
+ }"
+
+ register "SerialIoGSpiCsMode" = "{
+ [PchSerialIoIndexGSPI0] = 0,
+ [PchSerialIoIndexGSPI1] = 0,
+ [PchSerialIoIndexGSPI2] = 0,
+ [PchSerialIoIndexGSPI3] = 0,
+ }"
+
+ register "SerialIoGSpiCsState" = "{
+ [PchSerialIoIndexGSPI0] = 0,
+ [PchSerialIoIndexGSPI1] = 0,
+ [PchSerialIoIndexGSPI2] = 0,
+ [PchSerialIoIndexGSPI3] = 0,
+ }"
+
+ register "SerialIoUartMode" = "{
+ [PchSerialIoIndexUART0] = PchSerialIoDisabled,
+ [PchSerialIoIndexUART1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUART2] = PchSerialIoPci,
+ }"
+
+ #HD Audio
+ register "PchHdaDspEnable" = "1"
+ register "PchHdaAudioLinkHdaEnable" = "0"
+ register "PchHdaAudioLinkDmicEnable[0]" = "1"
+ register "PchHdaAudioLinkDmicEnable[1]" = "1"
+ register "PchHdaAudioLinkSspEnable[0]" = "1"
+ register "PchHdaAudioLinkSspEnable[1]" = "1"
+ # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T
+ register "PchHdaIDispLinkTmode" = "2"
+ # iDisp-Link Freq 4: 96MHz, 3: 48MHz.
+ register "PchHdaIDispLinkFrequency" = "4"
+ # Not disconnected/enumerable
+ register "PchHdaIDispCodecDisconnect" = "0"
+
+ device domain 0 on
+ #From EDS(575683)
+ device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y
+ device pci 02.0 on end # Graphics
+ device pci 04.0 on end # DPTF 0x9A03
+ device pci 05.0 on end # IPU 0x9A19
+ device pci 06.0 on end # PEG60 0x9A09
+ device pci 07.0 off end # TBT_PCIe0 0x9A23
+ device pci 07.1 off end # TBT_PCIe1 0x9A25
+ device pci 07.2 off end # TBT_PCIe2 0x9A27
+ device pci 07.3 off end # TBT_PCIe3 0x9A29
+ device pci 08.0 off end # GNA 0x9A11
+ device pci 09.0 off end # NPK 0x9A33
+ device pci 0a.0 off end # Crash-log SRAM 0x9A0D
+ device pci 0d.0 on end # USB xHCI 0x9A13
+ device pci 0d.1 on end # USB xDCI (OTG) 0x9A15
+ device pci 0d.2 off end # TBT DMA0 0x9A1B
+ device pci 0d.3 off end # TBT DMA1 0x9A1D
+ device pci 0e.0 on end # VMD 0x9A0B
+
+ # From PCH EDS(576591)
+ device pci 10.2 off end # CNVi: BT 0xA0F5 - A0F7
+ device pci 10.6 off end # THC0 0xA0D0
+ device pci 10.7 off end # THC1 0xA0D1
+ device pci 12.0 off end # SensorHUB 0xA0FC
+ device pci 12.6 off end # GSPI2 0x34FB
+ device pci 13.0 off end # GSPI3 0xA0FD
+ device pci 14.0 on end # USB3.1 xHCI 0xA0ED
+ device pci 14.1 on end # USB3.1 xDCI 0xA0EE
+ device pci 14.2 on end # Shared RAM 0xA0EF
+ device pci 14.3 off end # CNVi: WiFi 0xA0F0 - A0F3
+ device pci 15.0 on # I2C0 0xA0E8
+ chip drivers/i2c/max98373
+ register "vmon_slot_no" = "4"
+ register "imon_slot_no" = "5"
+ register "uid" = "0"
+ register "desc" = ""RIGHT SPEAKER AMP""
+ register "name" = ""MAXR""
+ device i2c 31 on end
+ end
+ chip drivers/i2c/max98373
+ register "vmon_slot_no" = "6"
+ register "imon_slot_no" = "7"
+ register "uid" = "1"
+ register "desc" = ""LEFT SPEAKER AMP""
+ register "name" = ""MAXL""
+ device i2c 32 on end
+ end
+ chip drivers/i2c/generic
+ register "hid" = ""10EC5682""
+ register "name" = ""RT58""
+ register "desc" = ""Realtek RT5682""
+ register "irq" = "ACPI_IRQ_EDGE_HIGH(GPP_C12_IRQ)"
+ register "probed" = "1"
+ # Set the jd_src to RT5668_JD1 for jack detection
+ register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+ register "property_list[0].name" = ""realtek,jd-src""
+ register "property_list[0].integer" = "1"
+ device i2c 1a on end
+ end
+ end # I2C0
+ device pci 15.1 on end # I2C1 0xA0E9
+ device pci 15.2 on end # I2C2 0xA0EA
+ device pci 15.3 on end # I2C3 0xA0EB
+ device pci 16.0 on end # HECI1 0xA0E0
+ device pci 16.1 off end # HECI2 0xA0E1
+ device pci 16.2 off end # CSME 0xA0E2
+ device pci 16.3 off end # CSME 0xA0E3
+ device pci 16.4 off end # HECI3 0xA0E4
+ device pci 16.5 off end # HECI4 0xA0E5
+ device pci 17.0 on end # SATA 0xA0D3
+ device pci 19.0 off end # I2C4 0xA0C5
+ device pci 19.1 on end # I2C5 0xA0C6
+ device pci 19.2 on end # UART2 0xA0C7
+ device pci 1c.0 off end # RP1 0xA0B8
+ device pci 1c.1 off end # RP2 0xA0B9
+ device pci 1c.2 on end # RP3 0xA0BA
+ device pci 1c.3 on end # RP4 0xA0BB
+ device pci 1c.4 off end # RP5 0xA0BC
+ device pci 1c.5 off end # RP6 0xA0BD
+ device pci 1c.6 off end # RP7 0xA0BE
+ device pci 1c.7 off end # RP8 0xA0BF
+ device pci 1d.0 on end # RP9 0xA0B0
+ device pci 1d.1 off end # RP10 0xA0B1
+ device pci 1d.2 on end # RP11 0xA0B2
+ device pci 1d.3 off end # RP12 0xA0B3
+ device pci 1e.0 off end # UART0 0xA0A8
+ device pci 1e.1 off end # UART1 0xA0A9
+ device pci 1e.2 off end # GSPI0 0xA0AA
+ device pci 1e.3 off end # GSPI1 0xA0AB
+ device pci 1f.0 on end # eSPI 0xA080 - A09F
+ device pci 1f.1 on end # P2SB 0xA0A0
+ device pci 1f.2 on end # PMC 0xA0A1
+ device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF
+ device pci 1f.4 on end # SMBus 0xA0A3
+ device pci 1f.5 on end # SPI 0xA0A4
+ device pci 1f.6 off end # GbE 0x15E1/0x15E2
+ device pci 1f.7 off end # TH 0xA0A6
+ end
+end