commit 6975e07997cedf8a78f0704a461765dfe2a09fe6
author Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Thu Mar 12 01:22:01 2020 -0700
committer Patrick Georgi <pgeorgi@google.com> Mon Mar 23 09:35:51 2020 +0000
tree 138b7bee3e2482d7a95ad4dfb9bf0d401f7b97f0
parent 79a219813b3e8186f5e89b2e0cd9f8a921fa088f

mb/tglrvp: Update Audio AIC settings for Tiger Lake

Update Audio AIC UPD settings and gpio pad configs for Tiger Lake.

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I45935b79f6fa4ad66238eead9258a4f15feec508
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>

src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb

diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index 586fd26..f2e5510 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -97,7 +97,9 @@
 	register "PchHdaAudioLinkDmicEnable[0]" = "1"
 	register "PchHdaAudioLinkDmicEnable[1]" = "1"
 	register "PchHdaAudioLinkSspEnable[0]" = "1"
-	register "PchHdaAudioLinkSspEnable[1]" = "1"
+	register "PchHdaAudioLinkSspEnable[1]" = "0"
+	register "PchHdaAudioLinkSspEnable[2]" = "1"
+	register "PchHdaAudioLinkSndwEnable[0]" = "1"
 	# iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T
 	register "PchHdaIDispLinkTmode" = "2"
 	# iDisp-Link Freq 4: 96MHz, 3: 48MHz.