Elyes HAOUAS | 36787b0 | 2020-05-07 12:07:24 +0200 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 2 | |
Kyösti Mälkki | eb5e28f | 2012-02-24 16:08:18 +0200 | [diff] [blame] | 3 | config NORTHBRIDGE_INTEL_I945 |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 4 | bool |
Kyösti Mälkki | eb5e28f | 2012-02-24 16:08:18 +0200 | [diff] [blame] | 5 | |
| 6 | if NORTHBRIDGE_INTEL_I945 |
| 7 | |
Elyes HAOUAS | 00b5f53 | 2021-02-01 09:45:08 +0100 | [diff] [blame] | 8 | config NORTHBRIDGE_SPECIFIC_OPTIONS |
Kyösti Mälkki | eb5e28f | 2012-02-24 16:08:18 +0200 | [diff] [blame] | 9 | def_bool y |
Jens Rottmann | 0d11f2d | 2010-08-26 12:46:02 +0000 | [diff] [blame] | 10 | select HAVE_DEBUG_RAM_SETUP |
Paul Menzel | ea8f3b4 | 2014-09-21 12:21:36 +0200 | [diff] [blame] | 11 | select VGA |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 12 | select INTEL_GMA_ACPI |
Nico Huber | 561bebf | 2017-01-19 16:28:18 +0100 | [diff] [blame] | 13 | select INTEL_GMA_SSC_ALTERNATE_REF |
Patrick Rudolph | 46cf5c2 | 2017-04-03 19:09:45 +0200 | [diff] [blame] | 14 | select INTEL_EDID |
Nico Huber | ce642f0 | 2017-05-19 15:08:21 +0200 | [diff] [blame] | 15 | select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT |
Uwe Hermann | 81b3c0a | 2009-10-30 12:56:59 +0000 | [diff] [blame] | 16 | |
Arthur Heymans | 48d5b8d | 2020-04-09 11:44:37 +0200 | [diff] [blame] | 17 | config VBOOT |
| 18 | select VBOOT_STARTS_IN_BOOTBLOCK |
Kyösti Mälkki | eb5e28f | 2012-02-24 16:08:18 +0200 | [diff] [blame] | 19 | config NORTHBRIDGE_INTEL_SUBTYPE_I945GC |
| 20 | def_bool n |
| 21 | config NORTHBRIDGE_INTEL_SUBTYPE_I945GM |
| 22 | def_bool n |
Peter Stuge | e4bc0f6 | 2010-10-01 09:13:18 +0000 | [diff] [blame] | 23 | |
Stefan Reinauer | bccbbe6 | 2010-12-19 21:20:14 +0000 | [diff] [blame] | 24 | config VGA_BIOS_ID |
Uwe Hermann | 81b3c0a | 2009-10-30 12:56:59 +0000 | [diff] [blame] | 25 | string |
Arthur Heymans | a6b0fc9 | 2016-10-16 17:20:35 +0200 | [diff] [blame] | 26 | default "8086,27a2" if NORTHBRIDGE_INTEL_SUBTYPE_I945GM |
| 27 | default "8086,2772" if NORTHBRIDGE_INTEL_SUBTYPE_I945GC |
Patrick Georgi | 77d6683 | 2010-10-01 08:02:45 +0000 | [diff] [blame] | 28 | |
Nico Huber | 7971582e | 2017-05-20 01:07:48 +0200 | [diff] [blame] | 29 | config I945_LVDS |
| 30 | def_bool n |
| 31 | select MAINBOARD_HAS_NATIVE_VGA_INIT |
| 32 | select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT |
| 33 | help |
| 34 | Selected by mainboards that use native graphics initialization |
| 35 | for the LVDS port. A linear framebuffer is only supported for |
| 36 | LVDS. |
| 37 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 38 | config ECAM_MMCONF_BASE_ADDRESS |
Arthur Heymans | c5fba2c | 2017-05-10 11:33:44 +0200 | [diff] [blame] | 39 | default 0xf0000000 |
| 40 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 41 | config ECAM_MMCONF_BUS_NUMBER |
Angel Pons | a6b0922 | 2021-01-20 13:00:02 +0100 | [diff] [blame] | 42 | int |
| 43 | default 64 |
| 44 | |
Patrick Georgi | 77d6683 | 2010-10-01 08:02:45 +0000 | [diff] [blame] | 45 | config OVERRIDE_CLOCK_DISABLE |
| 46 | bool |
| 47 | default n |
Patrick Georgi | 77d6683 | 2010-10-01 08:02:45 +0000 | [diff] [blame] | 48 | help |
| 49 | Usually system firmware turns off system memory clock |
| 50 | signals to unused SO-DIMM slots to reduce EMI and power |
| 51 | consumption. |
| 52 | However, some boards do not like unused clock signals to |
| 53 | be disabled. |
| 54 | |
| 55 | config MAXIMUM_SUPPORTED_FREQUENCY |
| 56 | int |
| 57 | default 0 |
Patrick Georgi | 77d6683 | 2010-10-01 08:02:45 +0000 | [diff] [blame] | 58 | help |
| 59 | If non-zero, this designates the maximum DDR frequency |
| 60 | the board supports, despite what the chipset should be |
| 61 | capable of. |
Peter Stuge | e4bc0f6 | 2010-10-01 09:13:18 +0000 | [diff] [blame] | 62 | |
Peter Stuge | 751508a | 2012-01-27 22:17:09 +0100 | [diff] [blame] | 63 | config CHECK_SLFRCS_ON_RESUME |
| 64 | def_bool n |
| 65 | help |
Martin Roth | 50863da | 2021-10-01 14:37:30 -0600 | [diff] [blame] | 66 | On some boards it may be necessary to hard reset early |
Peter Stuge | 751508a | 2012-01-27 22:17:09 +0100 | [diff] [blame] | 67 | during resume from S3 if the SLFRCS register indicates that |
| 68 | a memory channel is not guaranteed to be in self-refresh. |
| 69 | On other boards the check always creates a false positive, |
| 70 | effectively making it impossible to resume. |
| 71 | |
Arthur Heymans | dce3927 | 2018-04-10 16:08:27 +0200 | [diff] [blame] | 72 | config SMM_RESERVED_SIZE |
| 73 | hex |
| 74 | default 0x100000 |
| 75 | |
Angel Pons | f3973bd | 2020-05-29 01:17:16 +0200 | [diff] [blame] | 76 | config MAX_CPUS |
| 77 | int |
| 78 | default 4 |
| 79 | |
Angel Pons | 4299cb4 | 2021-01-20 12:32:22 +0100 | [diff] [blame] | 80 | config FIXED_MCHBAR_MMIO_BASE |
| 81 | default 0xfed14000 |
| 82 | |
| 83 | config FIXED_DMIBAR_MMIO_BASE |
| 84 | default 0xfed18000 |
| 85 | |
| 86 | config FIXED_EPBAR_MMIO_BASE |
| 87 | default 0xfed19000 |
| 88 | |
Peter Stuge | e4bc0f6 | 2010-10-01 09:13:18 +0000 | [diff] [blame] | 89 | endif |