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Stefan Reinauer36a22682008-10-29 04:52:57 +00001/*
2 * This file is part of the coreboot project.
3 *
Stefan Reinauerde3206a2010-02-22 06:09:43 +00004 * Copyright (C) 2007-2010 coresystems GmbH
Stefan Reinauer36a22682008-10-29 04:52:57 +00005 *
Uwe Hermann2bb4acf2010-03-01 17:19:55 +00006 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
Stefan Reinauer36a22682008-10-29 04:52:57 +00009 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
Uwe Hermann2bb4acf2010-03-01 17:19:55 +000017 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Stefan Reinauer36a22682008-10-29 04:52:57 +000018 */
19
Myles Watson1d6d45e2009-11-06 17:02:51 +000020// __PRE_RAM__ means: use "unsigned" for device, not a struct.
Stefan Reinauer5e328232010-03-29 19:19:16 +000021
Stefan Reinauer67cd8022010-01-16 16:35:38 +000022/* Configuration of the i945 driver */
23#define CHIPSET_I945GM 1
24/* Usually system firmware turns off system memory clock signals to
25 * unused SO-DIMM slots to reduce EMI and power consumption.
26 * However, the Kontron 986LCD-M does not like unused clock signals to
27 * be disabled. If other similar mainboard occur, it would make sense
28 * to make this an entry in the sysinfo structure, and pre-initialize that
Stefan Reinauer38f147e2010-02-08 12:20:50 +000029 * structure in the mainboard's romstage.c main() function. For now a
Stefan Reinauer67cd8022010-01-16 16:35:38 +000030 * #define will do.
31 */
32#define OVERRIDE_CLOCK_DISABLE 1
33#define CHANNEL_XOR_RANDOMIZATION 1
34
Stefan Reinauer36a22682008-10-29 04:52:57 +000035#include <stdint.h>
Patrick Georgi12aba822009-04-30 07:07:22 +000036#include <string.h>
Stefan Reinauer36a22682008-10-29 04:52:57 +000037#include <arch/io.h>
38#include <arch/romcc_io.h>
39#include <device/pci_def.h>
40#include <device/pnp_def.h>
41#include <cpu/x86/lapic.h>
42
43#include "superio/winbond/w83627thg/w83627thg.h"
44
45#include "option_table.h"
46#include "pc80/mc146818rtc_early.c"
47
Stefan Reinauerde3206a2010-02-22 06:09:43 +000048#include <console/console.h>
Stefan Reinauer36a22682008-10-29 04:52:57 +000049#include "pc80/serial.c"
Stefan Reinauer5a1f5972010-03-31 14:34:40 +000050#include "console/console.c"
Stefan Reinauer36a22682008-10-29 04:52:57 +000051#include <cpu/x86/bist.h>
52
Stefan Reinauera5fdadf2009-07-21 21:58:20 +000053#if CONFIG_USBDEBUG_DIRECT
54#define DBGP_DEFAULT 1
55#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
56#include "pc80/usbdebug_direct_serial.c"
57#endif
58
Stefan Reinauerc13093b2009-09-23 18:51:03 +000059#include "lib/ramtest.c"
Stefan Reinauer36a22682008-10-29 04:52:57 +000060#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
Stefan Reinauer36a22682008-10-29 04:52:57 +000061#include "superio/winbond/w83627thg/w83627thg_early_serial.c"
62
63#include "northbridge/intel/i945/udelay.c"
64
Stefan Reinauer36a22682008-10-29 04:52:57 +000065#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
66
Stefan Reinauera5fdadf2009-07-21 21:58:20 +000067#include "southbridge/intel/i82801gx/i82801gx.h"
Stefan Reinauer36a22682008-10-29 04:52:57 +000068static void setup_ich7_gpios(void)
69{
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +000070 printk(BIOS_DEBUG, " GPIOS...");
Stefan Reinauer36a22682008-10-29 04:52:57 +000071 /* General Registers */
72 outl(0x1f1ff7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
73 outl(0xe0e8efc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
74 outl(0xebffeeff, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
75 /* Output Control Registers */
76 outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
77 /* Input Control Registers */
78 outl(0x00002180, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
Stefan Reinauere1025d02009-03-11 15:20:36 +000079 outl(0x000100ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
Stefan Reinauer36a22682008-10-29 04:52:57 +000080 outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
81 outl(0x00010035, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */
82}
83
84#include "northbridge/intel/i945/early_init.c"
85
86static inline int spd_read_byte(unsigned device, unsigned address)
87{
88 return smbus_read_byte(device, address);
89}
90
Stefan Reinauer36a22682008-10-29 04:52:57 +000091#include "northbridge/intel/i945/raminit.h"
92#include "northbridge/intel/i945/raminit.c"
Stefan Reinauer36a22682008-10-29 04:52:57 +000093#include "northbridge/intel/i945/errata.c"
Stefan Reinauer67cd8022010-01-16 16:35:38 +000094#include "northbridge/intel/i945/debug.c"
Stefan Reinauer36a22682008-10-29 04:52:57 +000095
96static void ich7_enable_lpc(void)
97{
98 // Enable Serial IRQ
99 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
100 // Set COM1/COM2 decode range
101 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
102 // Enable COM1/COM2/KBD/SuperIO1+2
103 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b);
104 // Enable HWM at 0xa00
Stefan Reinauere1025d02009-03-11 15:20:36 +0000105 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0a01);
Stefan Reinauer36a22682008-10-29 04:52:57 +0000106 // COM3 decode
107 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9);
108 // COM4 decode
109 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000402e9);
110 // io 0x300 decode
111 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301);
112}
113
Stefan Reinauer36a22682008-10-29 04:52:57 +0000114/* This box has two superios, so enabling serial becomes slightly excessive.
115 * We disable a lot of stuff to make sure that there are no conflicts between
116 * the two. Also set up the GPIOs from the beginning. This is the "no schematic
117 * but safe anyways" method.
118 */
119static void early_superio_config_w83627thg(void)
120{
121 device_t dev;
122
123 dev=PNP_DEV(0x2e, W83627THG_SP1);
124 pnp_enter_ext_func_mode(dev);
125
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000126 pnp_write_config(dev, 0x24, 0xc6); // PNPCSV
127
128 pnp_write_config(dev, 0x29, 0x43); // GPIO settings
129 pnp_write_config(dev, 0x2a, 0x40); // GPIO settings
130
131 dev=PNP_DEV(0x2e, W83627THG_SP1);
Stefan Reinauer36a22682008-10-29 04:52:57 +0000132 pnp_set_logical_device(dev);
133 pnp_set_enable(dev, 0);
134 pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
135 pnp_set_irq(dev, PNP_IDX_IRQ0, 4);
136 pnp_set_enable(dev, 1);
137
138 dev=PNP_DEV(0x2e, W83627THG_SP2);
139 pnp_set_logical_device(dev);
140 pnp_set_enable(dev, 0);
141 pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8);
142 pnp_set_irq(dev, PNP_IDX_IRQ0, 3);
143 // pnp_write_config(dev, 0xf1, 4); // IRMODE0
144 pnp_set_enable(dev, 1);
145
146 dev=PNP_DEV(0x2e, W83627THG_KBC);
147 pnp_set_logical_device(dev);
148 pnp_set_enable(dev, 0);
149 pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
150 pnp_set_iobase(dev, PNP_IDX_IO1, 0x64);
151 // pnp_write_config(dev, 0xf0, 0x82);
152 pnp_set_enable(dev, 1);
153
154 dev=PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1);
155 pnp_set_logical_device(dev);
156 pnp_set_enable(dev, 0);
157 pnp_write_config(dev, 0xf5, 0xff); // invert all GPIOs
158 pnp_set_enable(dev, 1);
159
160 dev=PNP_DEV(0x2e, W83627THG_GPIO2);
161 pnp_set_logical_device(dev);
162 pnp_set_enable(dev, 1); // Just enable it
163
164 dev=PNP_DEV(0x2e, W83627THG_GPIO3);
165 pnp_set_logical_device(dev);
166 pnp_set_enable(dev, 0);
167 pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output
168 pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0
169 pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient
170
171 dev=PNP_DEV(0x2e, W83627THG_FDC);
172 pnp_set_logical_device(dev);
173 pnp_set_enable(dev, 0);
174
175 dev=PNP_DEV(0x2e, W83627THG_PP);
176 pnp_set_logical_device(dev);
177 pnp_set_enable(dev, 0);
178
Stefan Reinauer54309d62009-01-20 22:53:10 +0000179 /* Enable HWM */
180 dev=PNP_DEV(0x2e, W83627THG_HWM);
181 pnp_set_logical_device(dev);
182 pnp_set_enable(dev, 0);
183 pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00);
184 pnp_set_enable(dev, 1);
185
Stefan Reinauer36a22682008-10-29 04:52:57 +0000186 pnp_exit_ext_func_mode(dev);
187
188 dev=PNP_DEV(0x4e, W83627THG_SP1);
189 pnp_enter_ext_func_mode(dev);
190
191 pnp_set_logical_device(dev); // Set COM3 to sane non-conflicting values
192 pnp_set_enable(dev, 0);
193 pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8);
194 pnp_set_irq(dev, PNP_IDX_IRQ0, 11);
195 pnp_set_enable(dev, 1);
196
197 dev=PNP_DEV(0x4e, W83627THG_SP2);
198 pnp_set_logical_device(dev); // Set COM4 to sane non-conflicting values
199 pnp_set_enable(dev, 0);
200 pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8);
201 pnp_set_irq(dev, PNP_IDX_IRQ0, 10);
202 pnp_set_enable(dev, 1);
203
204 dev=PNP_DEV(0x4e, W83627THG_FDC);
205 pnp_set_logical_device(dev);
206 pnp_set_enable(dev, 0);
207
208 dev=PNP_DEV(0x4e, W83627THG_PP);
209 pnp_set_logical_device(dev);
210 pnp_set_enable(dev, 0);
211
212 dev=PNP_DEV(0x4e, W83627THG_KBC);
213 pnp_set_logical_device(dev);
214 pnp_set_enable(dev, 0);
215 pnp_set_iobase(dev, PNP_IDX_IO0, 0x00);
216 pnp_set_iobase(dev, PNP_IDX_IO1, 0x00);
217
218 pnp_exit_ext_func_mode(dev);
219}
220
221static void rcba_config(void)
222{
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000223 u32 reg32;
224
Stefan Reinauer36a22682008-10-29 04:52:57 +0000225 /* Set up virtual channel 0 */
226 //RCBA32(0x0014) = 0x80000001;
227 //RCBA32(0x001c) = 0x03128010;
228
229 /* Device 1f interrupt pin register */
230 RCBA32(0x3100) = 0x00042210;
231 /* Device 1d interrupt pin register */
232 RCBA32(0x310c) = 0x00214321;
233
234 /* dev irq route register */
235 RCBA16(0x3140) = 0x0132;
236 RCBA16(0x3142) = 0x3241;
237 RCBA16(0x3144) = 0x0237;
238 RCBA16(0x3146) = 0x3210;
239 RCBA16(0x3148) = 0x3210;
240
241 /* Enable IOAPIC */
242 RCBA8(0x31ff) = 0x03;
243
244 /* Enable upper 128bytes of CMOS */
245 RCBA32(0x3400) = (1 << 2);
246
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000247 /* Now, this is a bit ugly. As per PCI specification, function 0 of a
248 * device always has to be implemented. So disabling ethernet port 1
249 * would essentially disable all three ethernet ports of the mainboard.
250 * It's possible to rename the ports to achieve compatibility to the
251 * PCI spec but this will confuse all (static!) tables containing
252 * interrupt routing information.
253 * To avoid this, we enable (unused) port 6 and swap it with port 1
254 * in the case that ethernet port 1 is disabled. Since no devices
255 * are connected to that port, we don't have to worry about interrupt
256 * routing.
257 */
258 int port_shuffle = 0;
259
Stefan Reinauer36a22682008-10-29 04:52:57 +0000260 /* Disable unused devices */
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000261 reg32 = FD_ACMOD|FD_ACAUD|FD_PATA;
262 reg32 |= FD_PCIE6|FD_PCIE5|FD_PCIE4;
263
264 if (read_option(CMOS_VSTART_ethernet1, CMOS_VLEN_ethernet1, 0) != 0) {
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000265 printk(BIOS_DEBUG, "Disabling ethernet adapter 1.\n");
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000266 reg32 |= FD_PCIE1;
267 }
268 if (read_option(CMOS_VSTART_ethernet2, CMOS_VLEN_ethernet2, 0) != 0) {
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000269 printk(BIOS_DEBUG, "Disabling ethernet adapter 2.\n");
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000270 reg32 |= FD_PCIE2;
271 } else {
272 if (reg32 & FD_PCIE1)
273 port_shuffle = 1;
274 }
275 if (read_option(CMOS_VSTART_ethernet3, CMOS_VLEN_ethernet3, 0) != 0) {
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000276 printk(BIOS_DEBUG, "Disabling ethernet adapter 3.\n");
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000277 reg32 |= FD_PCIE3;
278 } else {
279 if (reg32 & FD_PCIE1)
280 port_shuffle = 1;
281 }
282
283 if (port_shuffle) {
284 /* Enable PCIE6 again */
285 reg32 &= ~FD_PCIE6;
286 /* Swap PCIE6 and PCIE1 */
287 RCBA32(RPFN) = 0x00043215;
288 }
289
290 reg32 |= 1;
291
292 RCBA32(0x3418) = reg32;
Stefan Reinauer36a22682008-10-29 04:52:57 +0000293
294 /* Enable PCIe Root Port Clock Gate */
295 // RCBA32(0x341c) = 0x00000001;
296}
297
298static void early_ich7_init(void)
299{
300 uint8_t reg8;
301 uint32_t reg32;
302
303 // program secondary mlt XXX byte?
304 pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
305
306 // reset rtc power status
307 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
308 reg8 &= ~(1 << 2);
309 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
310
311 // usb transient disconnect
312 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
313 reg8 |= (3 << 0);
314 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
315
316 reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
317 reg32 |= (1 << 29) | (1 << 17);
318 pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
319
320 reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
321 reg32 |= (1 << 31) | (1 << 27);
322 pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
323
324 RCBA32(0x0088) = 0x0011d000;
325 RCBA16(0x01fc) = 0x060f;
326 RCBA32(0x01f4) = 0x86000040;
327 RCBA32(0x0214) = 0x10030549;
328 RCBA32(0x0218) = 0x00020504;
329 RCBA8(0x0220) = 0xc5;
330 reg32 = RCBA32(0x3410);
331 reg32 |= (1 << 6);
332 RCBA32(0x3410) = reg32;
333 reg32 = RCBA32(0x3430);
334 reg32 &= ~(3 << 0);
335 reg32 |= (1 << 0);
336 RCBA32(0x3430) = reg32;
337 RCBA32(0x3418) |= (1 << 0);
338 RCBA16(0x0200) = 0x2008;
339 RCBA8(0x2027) = 0x0d;
340 RCBA16(0x3e08) |= (1 << 7);
341 RCBA16(0x3e48) |= (1 << 7);
342 RCBA32(0x3e0e) |= (1 << 7);
343 RCBA32(0x3e4e) |= (1 << 7);
344
345 // next step only on ich7m b0 and later:
346 reg32 = RCBA32(0x2034);
347 reg32 &= ~(0x0f << 16);
348 reg32 |= (5 << 16);
349 RCBA32(0x2034) = reg32;
350}
351
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000352#include <cbmem.h>
353
354// Now, this needs to be included because it relies on the symbol
Myles Watson1d6d45e2009-11-06 17:02:51 +0000355// __PRE_RAM__ being set during CAR stage (in order to compile the
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000356// BSS free versions of the functions). Either rewrite the code
357// to be always BSS free, or invent a flag that's better suited than
Myles Watson1d6d45e2009-11-06 17:02:51 +0000358// __PRE_RAM__ to determine whether we're in ram init stage (stage 1)
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000359//
360#include "lib/cbmem.c"
361
Stefan Reinauer3e1f5242010-04-12 23:04:29 +0000362void main(unsigned long bist)
Stefan Reinauer36a22682008-10-29 04:52:57 +0000363{
Stefan Reinauera5fdadf2009-07-21 21:58:20 +0000364 u32 reg32;
Stefan Reinauer36a22682008-10-29 04:52:57 +0000365 int boot_mode = 0;
366
367 if (bist == 0) {
368 enable_lapic();
369 }
370
371 ich7_enable_lpc();
372 early_superio_config_w83627thg();
373
374 /* Set up the console */
375 uart_init();
Stefan Reinauera5fdadf2009-07-21 21:58:20 +0000376
377#if CONFIG_USBDEBUG_DIRECT
378 i82801gx_enable_usbdebug_direct(DBGP_DEFAULT);
379 early_usbdebug_direct_init();
380#endif
381
Stefan Reinauer36a22682008-10-29 04:52:57 +0000382 console_init();
383
384 /* Halt if there was a built in self test failure */
385 report_bist_failure(bist);
386
387 if (MCHBAR16(SSKPD) == 0xCAFE) {
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000388 printk(BIOS_DEBUG, "soft reset detected.\n");
Stefan Reinauer36a22682008-10-29 04:52:57 +0000389 boot_mode = 1;
390 }
391
392 /* Perform some early chipset initialization required
393 * before RAM initialization can work
394 */
395 i945_early_initialization();
396
Stefan Reinauera5fdadf2009-07-21 21:58:20 +0000397 /* Read PM1_CNT */
398 reg32 = inl(DEFAULT_PMBASE + 0x04);
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000399 printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
Stefan Reinauera5fdadf2009-07-21 21:58:20 +0000400 if (((reg32 >> 10) & 7) == 5) {
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000401#if CONFIG_HAVE_ACPI_RESUME
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000402 printk(BIOS_DEBUG, "Resume from S3 detected.\n");
Stefan Reinauera5fdadf2009-07-21 21:58:20 +0000403 boot_mode = 2;
404 /* Clear SLP_TYPE. This will break stage2 but
405 * we care for that when we get there.
406 */
407 outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000408
Stefan Reinauera5fdadf2009-07-21 21:58:20 +0000409#else
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000410 printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
Stefan Reinauera5fdadf2009-07-21 21:58:20 +0000411#endif
412 }
413
Stefan Reinauer36a22682008-10-29 04:52:57 +0000414 /* Enable SPD ROMs and DDR-II DRAM */
415 enable_smbus();
416
Stefan Reinauer08670622009-06-30 15:17:49 +0000417#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
Stefan Reinauer36a22682008-10-29 04:52:57 +0000418 dump_spd_registers();
419#endif
420
421 sdram_initialize(boot_mode);
422
423 /* Perform some initialization that must run before stage2 */
424 early_ich7_init();
425
426 /* This should probably go away. Until now it is required
427 * and mainboard specific
428 */
429 rcba_config();
430
431 /* Chipset Errata! */
432 fixup_i945_errata();
433
434 /* Initialize the internal PCIe links before we go into stage2 */
435 i945_late_initialization();
436
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000437#if !CONFIG_HAVE_ACPI_RESUME
Stefan Reinauer08670622009-06-30 15:17:49 +0000438#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
Uwe Hermann01ce6012010-03-05 10:03:50 +0000439#if CONFIG_DEBUG_RAM_SETUP
Stefan Reinauer36a22682008-10-29 04:52:57 +0000440 sdram_dump_mchbar_registers();
441#endif
442
443 {
444 /* This will not work if TSEG is in place! */
445 u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
446
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000447 printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
Stefan Reinauer36a22682008-10-29 04:52:57 +0000448 ram_check(0x00000000, 0x000a0000);
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000449 //ram_check(0x00100000, tom);
Stefan Reinauer36a22682008-10-29 04:52:57 +0000450 }
451#endif
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000452#endif
453
Stefan Reinauere0d607a2010-03-28 21:31:30 +0000454 quick_ram_check();
455
Stefan Reinauer36a22682008-10-29 04:52:57 +0000456 MCHBAR16(SSKPD) = 0xCAFE;
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000457
458#if CONFIG_HAVE_ACPI_RESUME
459 /* Start address of high memory tables */
460 unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
461
462 /* If there is no high memory area, we didn't boot before, so
463 * this is not a resume. In that case we just create the cbmem toc.
464 */
465 if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) {
466 void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
467
468 /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
469 * through stage 2. We could keep stuff like stack and heap in high tables
470 * memory completely, but that's a wonderful clean up task for another
471 * day.
472 */
473 if (resume_backup_memory)
Stefan Reinauerde3206a2010-02-22 06:09:43 +0000474 memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000475
476 /* Magic for S3 resume */
477 pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
478 }
479#endif
Stefan Reinauer36a22682008-10-29 04:52:57 +0000480}
481