Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 3 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 4 | #include <device/device.h> |
| 5 | #include <device/pci.h> |
| 6 | #include <device/pci_ids.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 7 | #include <device/smbus.h> |
Aaron Durbin | 178d644 | 2020-01-28 11:10:23 -0700 | [diff] [blame] | 8 | #include <device/smbus_host.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 9 | #include <cpu/x86/lapic.h> |
| 10 | #include <arch/ioapic.h> |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 11 | #include <soc/southbridge.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 12 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 13 | /* |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 14 | * The southbridge enables all USB controllers by default in SMBUS Control. |
| 15 | * The southbridge enables SATA by default in SMBUS Control. |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 16 | */ |
| 17 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 18 | static void sm_init(struct device *dev) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 19 | { |
| 20 | setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS); |
| 21 | } |
| 22 | |
Richard Spiegel | b40e193 | 2018-10-24 12:51:21 -0700 | [diff] [blame] | 23 | static u32 get_sm_mmio(struct device *dev) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 24 | { |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 25 | struct resource *res; |
| 26 | struct bus *pbus; |
| 27 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 28 | pbus = get_pbus_smbus(dev); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 29 | res = find_resource(pbus->dev, 0x90); |
Richard Spiegel | b40e193 | 2018-10-24 12:51:21 -0700 | [diff] [blame] | 30 | if (res->base == SMB_BASE_ADDR) |
Marshall Dawson | 5de4771 | 2019-05-01 16:14:42 -0600 | [diff] [blame] | 31 | return ACPIMMIO_SMBUS_BASE; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 32 | |
Marshall Dawson | 5de4771 | 2019-05-01 16:14:42 -0600 | [diff] [blame] | 33 | return ACPIMMIO_ASF_BASE; |
Richard Spiegel | b40e193 | 2018-10-24 12:51:21 -0700 | [diff] [blame] | 34 | } |
| 35 | |
| 36 | static int lsmbus_recv_byte(struct device *dev) |
| 37 | { |
| 38 | u8 device; |
| 39 | |
| 40 | device = dev->path.i2c.device; |
| 41 | return do_smbus_recv_byte(get_sm_mmio(dev), device); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 42 | } |
| 43 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 44 | static int lsmbus_send_byte(struct device *dev, u8 val) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 45 | { |
Richard Spiegel | cd04e31 | 2017-11-08 14:58:30 -0700 | [diff] [blame] | 46 | u8 device; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 47 | |
| 48 | device = dev->path.i2c.device; |
Richard Spiegel | b40e193 | 2018-10-24 12:51:21 -0700 | [diff] [blame] | 49 | return do_smbus_send_byte(get_sm_mmio(dev), device, val); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 50 | } |
| 51 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 52 | static int lsmbus_read_byte(struct device *dev, u8 address) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 53 | { |
Richard Spiegel | cd04e31 | 2017-11-08 14:58:30 -0700 | [diff] [blame] | 54 | u8 device; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 55 | |
| 56 | device = dev->path.i2c.device; |
Richard Spiegel | b40e193 | 2018-10-24 12:51:21 -0700 | [diff] [blame] | 57 | return do_smbus_read_byte(get_sm_mmio(dev), device, address); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 58 | } |
| 59 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 60 | static int lsmbus_write_byte(struct device *dev, u8 address, u8 val) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 61 | { |
Richard Spiegel | cd04e31 | 2017-11-08 14:58:30 -0700 | [diff] [blame] | 62 | u8 device; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 63 | |
| 64 | device = dev->path.i2c.device; |
Richard Spiegel | b40e193 | 2018-10-24 12:51:21 -0700 | [diff] [blame] | 65 | return do_smbus_write_byte(get_sm_mmio(dev), device, address, val); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 66 | } |
| 67 | static struct smbus_bus_operations lops_smbus_bus = { |
| 68 | .recv_byte = lsmbus_recv_byte, |
| 69 | .send_byte = lsmbus_send_byte, |
| 70 | .read_byte = lsmbus_read_byte, |
| 71 | .write_byte = lsmbus_write_byte, |
| 72 | }; |
| 73 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 74 | static struct pci_operations lops_pci = { |
| 75 | .set_subsystem = pci_dev_set_subsystem, |
| 76 | }; |
| 77 | static struct device_operations smbus_ops = { |
Richard Spiegel | cd04e31 | 2017-11-08 14:58:30 -0700 | [diff] [blame] | 78 | .read_resources = DEVICE_NOOP, |
| 79 | .set_resources = DEVICE_NOOP, |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 80 | .enable_resources = pci_dev_enable_resources, |
| 81 | .init = sm_init, |
| 82 | .scan_bus = scan_smbus, |
| 83 | .ops_pci = &lops_pci, |
| 84 | .ops_smbus_bus = &lops_smbus_bus, |
| 85 | }; |
| 86 | static const struct pci_driver smbus_driver __pci_driver = { |
| 87 | .ops = &smbus_ops, |
| 88 | .vendor = PCI_VENDOR_ID_AMD, |
Martin Roth | 069ca66 | 2018-03-01 11:26:18 -0700 | [diff] [blame] | 89 | .device = PCI_DEVICE_ID_AMD_CZ_SMBUS, |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 90 | }; |