Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <console/console.h> |
| 17 | #include <device/device.h> |
| 18 | #include <device/pci.h> |
| 19 | #include <device/pci_ids.h> |
| 20 | #include <device/pci_ops.h> |
| 21 | #include <device/smbus.h> |
| 22 | #include <pc80/mc146818rtc.h> |
| 23 | #include <arch/io.h> |
| 24 | #include <cpu/x86/lapic.h> |
| 25 | #include <arch/ioapic.h> |
| 26 | #include <stdlib.h> |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 27 | #include <soc/southbridge.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 28 | #include <soc/smbus.h> |
| 29 | |
| 30 | #define NMI_OFF 0 |
| 31 | |
| 32 | #define MAINBOARD_POWER_OFF 0 |
| 33 | #define MAINBOARD_POWER_ON 1 |
| 34 | |
| 35 | #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL |
| 36 | #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON |
| 37 | #endif |
| 38 | |
| 39 | /* |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 40 | * The southbridge enables all USB controllers by default in SMBUS Control. |
| 41 | * The southbridge enables SATA by default in SMBUS Control. |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 42 | */ |
| 43 | |
| 44 | static void sm_init(device_t dev) |
| 45 | { |
| 46 | setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS); |
| 47 | } |
| 48 | |
| 49 | static int lsmbus_recv_byte(device_t dev) |
| 50 | { |
Richard Spiegel | cd04e31 | 2017-11-08 14:58:30 -0700 | [diff] [blame^] | 51 | u8 device; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 52 | struct resource *res; |
| 53 | struct bus *pbus; |
| 54 | |
| 55 | device = dev->path.i2c.device; |
| 56 | pbus = get_pbus_smbus(dev); |
| 57 | |
| 58 | res = find_resource(pbus->dev, 0x90); |
| 59 | |
| 60 | return do_smbus_recv_byte(res->base, device); |
| 61 | } |
| 62 | |
| 63 | static int lsmbus_send_byte(device_t dev, u8 val) |
| 64 | { |
Richard Spiegel | cd04e31 | 2017-11-08 14:58:30 -0700 | [diff] [blame^] | 65 | u8 device; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 66 | struct resource *res; |
| 67 | struct bus *pbus; |
| 68 | |
| 69 | device = dev->path.i2c.device; |
| 70 | pbus = get_pbus_smbus(dev); |
| 71 | |
| 72 | res = find_resource(pbus->dev, 0x90); |
| 73 | |
| 74 | return do_smbus_send_byte(res->base, device, val); |
| 75 | } |
| 76 | |
| 77 | static int lsmbus_read_byte(device_t dev, u8 address) |
| 78 | { |
Richard Spiegel | cd04e31 | 2017-11-08 14:58:30 -0700 | [diff] [blame^] | 79 | u8 device; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 80 | struct resource *res; |
| 81 | struct bus *pbus; |
| 82 | |
| 83 | device = dev->path.i2c.device; |
| 84 | pbus = get_pbus_smbus(dev); |
| 85 | |
| 86 | res = find_resource(pbus->dev, 0x90); |
| 87 | |
| 88 | return do_smbus_read_byte(res->base, device, address); |
| 89 | } |
| 90 | |
| 91 | static int lsmbus_write_byte(device_t dev, u8 address, u8 val) |
| 92 | { |
Richard Spiegel | cd04e31 | 2017-11-08 14:58:30 -0700 | [diff] [blame^] | 93 | u8 device; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 94 | struct resource *res; |
| 95 | struct bus *pbus; |
| 96 | |
| 97 | device = dev->path.i2c.device; |
| 98 | pbus = get_pbus_smbus(dev); |
| 99 | |
| 100 | res = find_resource(pbus->dev, 0x90); |
| 101 | |
| 102 | return do_smbus_write_byte(res->base, device, address, val); |
| 103 | } |
| 104 | static struct smbus_bus_operations lops_smbus_bus = { |
| 105 | .recv_byte = lsmbus_recv_byte, |
| 106 | .send_byte = lsmbus_send_byte, |
| 107 | .read_byte = lsmbus_read_byte, |
| 108 | .write_byte = lsmbus_write_byte, |
| 109 | }; |
| 110 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 111 | static struct pci_operations lops_pci = { |
| 112 | .set_subsystem = pci_dev_set_subsystem, |
| 113 | }; |
| 114 | static struct device_operations smbus_ops = { |
Richard Spiegel | cd04e31 | 2017-11-08 14:58:30 -0700 | [diff] [blame^] | 115 | .read_resources = DEVICE_NOOP, |
| 116 | .set_resources = DEVICE_NOOP, |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 117 | .enable_resources = pci_dev_enable_resources, |
| 118 | .init = sm_init, |
| 119 | .scan_bus = scan_smbus, |
| 120 | .ops_pci = &lops_pci, |
| 121 | .ops_smbus_bus = &lops_smbus_bus, |
| 122 | }; |
| 123 | static const struct pci_driver smbus_driver __pci_driver = { |
| 124 | .ops = &smbus_ops, |
| 125 | .vendor = PCI_VENDOR_ID_AMD, |
| 126 | .device = PCI_DEVICE_ID_AMD_SB900_SM, |
| 127 | }; |