Angel Pons | 64b5d97 | 2020-04-05 13:20:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Matt DeVillier | 81ae67a | 2016-11-08 15:04:30 -0600 | [diff] [blame] | 2 | |
Angel Pons | d37b7d8 | 2020-07-03 23:52:34 +0200 | [diff] [blame] | 3 | #include <stdint.h> |
Matt DeVillier | 81ae67a | 2016-11-08 15:04:30 -0600 | [diff] [blame] | 4 | #include <northbridge/intel/haswell/haswell.h> |
| 5 | #include <northbridge/intel/haswell/raminit.h> |
Matt DeVillier | 81ae67a | 2016-11-08 15:04:30 -0600 | [diff] [blame] | 6 | #include <southbridge/intel/lynxpoint/pch.h> |
Matt DeVillier | 81ae67a | 2016-11-08 15:04:30 -0600 | [diff] [blame] | 7 | |
Angel Pons | 6e1c471 | 2020-07-03 13:05:10 +0200 | [diff] [blame] | 8 | void mainboard_config_rcba(void) |
| 9 | { |
Matt DeVillier | 81ae67a | 2016-11-08 15:04:30 -0600 | [diff] [blame] | 10 | /* |
| 11 | * GFX INTA -> PIRQA (MSI) |
| 12 | * D28IP_P1IP PCIE INTA -> PIRQA |
| 13 | * D29IP_E1P EHCI INTA -> PIRQD |
| 14 | * D20IP_XHCI XHCI INTA -> PIRQC (MSI) |
| 15 | * D31IP_SIP SATA INTA -> PIRQF (MSI) |
| 16 | * D31IP_SMIP SMBUS INTB -> PIRQG |
| 17 | * D31IP_TTIP THRT INTC -> PIRQA |
| 18 | * D27IP_ZIP HDA INTA -> PIRQG (MSI) |
| 19 | */ |
| 20 | |
| 21 | /* Device interrupt pin register (board specific) */ |
Angel Pons | 6e1c471 | 2020-07-03 13:05:10 +0200 | [diff] [blame] | 22 | RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | |
| 23 | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); |
| 24 | RCBA32(D29IP) = (INTA << D29IP_E1P); |
| 25 | RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | |
| 26 | (INTB << D28IP_P4IP); |
| 27 | RCBA32(D27IP) = (INTA << D27IP_ZIP); |
| 28 | RCBA32(D26IP) = (INTA << D26IP_E2P); |
| 29 | RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); |
| 30 | RCBA32(D20IP) = (INTA << D20IP_XHCI); |
Matt DeVillier | 81ae67a | 2016-11-08 15:04:30 -0600 | [diff] [blame] | 31 | |
| 32 | /* Device interrupt route registers */ |
Angel Pons | c05c2b3 | 2020-07-03 14:28:48 +0200 | [diff] [blame] | 33 | RCBA16(D31IR) = DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA); /* LPC */ |
| 34 | RCBA16(D29IR) = DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD); /* EHCI */ |
| 35 | RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); /* PCIE */ |
| 36 | RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG); /* HDA */ |
| 37 | RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); /* ME */ |
| 38 | RCBA16(D21IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF); /* SIO */ |
| 39 | RCBA16(D20IR) = DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC); /* XHCI */ |
| 40 | RCBA16(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */ |
Angel Pons | 6e1c471 | 2020-07-03 13:05:10 +0200 | [diff] [blame] | 41 | } |
Matt DeVillier | 81ae67a | 2016-11-08 15:04:30 -0600 | [diff] [blame] | 42 | |
Angel Pons | d37b7d8 | 2020-07-03 23:52:34 +0200 | [diff] [blame] | 43 | void mb_get_spd_map(uint8_t spd_map[4]) |
| 44 | { |
| 45 | spd_map[0] = 0xa0; |
| 46 | spd_map[2] = 0xa4; |
| 47 | } |
| 48 | |
Angel Pons | a3c6ed0 | 2021-02-11 13:59:12 +0100 | [diff] [blame^] | 49 | const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { |
| 50 | /* Length, Enable, OCn#, Location */ |
| 51 | { 0x0064, 1, 0, /* P0: VP8 */ |
| 52 | USB_PORT_MINI_PCIE }, |
| 53 | { 0x0040, 1, 0, /* P1: Port A, CN22 */ |
| 54 | USB_PORT_INTERNAL }, |
| 55 | { 0x0040, 1, 1, /* P2: Port B, CN23 */ |
| 56 | USB_PORT_INTERNAL }, |
| 57 | { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: WLAN */ |
| 58 | USB_PORT_INTERNAL }, |
| 59 | { 0x0040, 1, 2, /* P4: Port C, CN25 */ |
| 60 | USB_PORT_INTERNAL }, |
| 61 | { 0x0040, 1, 2, /* P5: Port D, CN25 */ |
| 62 | USB_PORT_INTERNAL }, |
| 63 | { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: Card Reader */ |
| 64 | USB_PORT_INTERNAL }, |
| 65 | { 0x0000, 0, 0, /* P7: N/C */ |
| 66 | USB_PORT_SKIP }, |
| 67 | }; |
Matt DeVillier | 81ae67a | 2016-11-08 15:04:30 -0600 | [diff] [blame] | 68 | |
Angel Pons | a3c6ed0 | 2021-02-11 13:59:12 +0100 | [diff] [blame^] | 69 | const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { |
| 70 | /* Enable, OCn# */ |
| 71 | { 1, 0 }, /* P1; CN22 */ |
| 72 | { 1, 1 }, /* P2; CN23 */ |
| 73 | { 1, 2 }, /* P3; CN25 */ |
| 74 | { 1, 2 }, /* P4; CN25 */ |
| 75 | }; |