Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 81ae67a634d3bd72b10f798490ee25c3a3cb807a / . / src / mainboard / google / beltino / romstage.c
blob: 2ddb9b12a89ee65916acfad0b339acfbc33d4805 [file] [log] [blame]
Matt DeVillier81ae67a2016-11-08 15:04:30 -0600[diff] [blame^]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2010 coresystems GmbH
5 * Copyright (C) 2012 Google Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <cbfs.h>
18#include <stdint.h>
19#include <stdlib.h>
20#include <string.h>
21#include <console/console.h>
22#include <cpu/intel/haswell/haswell.h>
23#include <northbridge/intel/haswell/haswell.h>
24#include <northbridge/intel/haswell/raminit.h>
25#include <southbridge/intel/lynxpoint/lp_gpio.h>
26#include <southbridge/intel/lynxpoint/pch.h>
27#include <superio/ite/common/ite.h>
28#include <superio/ite/it8772f/it8772f.h>
29#include <variant/gpio.h>
30#include "onboard.h"
31
32const struct rcba_config_instruction rcba_config[] = {
33
34 /*
35 * GFX INTA -> PIRQA (MSI)
36 * D28IP_P1IP PCIE INTA -> PIRQA
37 * D29IP_E1P EHCI INTA -> PIRQD
38 * D20IP_XHCI XHCI INTA -> PIRQC (MSI)
39 * D31IP_SIP SATA INTA -> PIRQF (MSI)
40 * D31IP_SMIP SMBUS INTB -> PIRQG
41 * D31IP_TTIP THRT INTC -> PIRQA
42 * D27IP_ZIP HDA INTA -> PIRQG (MSI)
43 */
44
45 /* Device interrupt pin register (board specific) */
46 RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
47 (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)),
48 RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)),
49 RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
50 (INTB << D28IP_P4IP)),
51 RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)),
52 RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)),
53 RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)),
54 RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)),
55
56 /* Device interrupt route registers */
57 RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */
58 RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */
59 RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */
60 RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */
61 RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */
62 RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */
63 RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */
64 RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */
65
66 /* Disable unused devices (board specific) */
67 RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS),
68
69 RCBA_END_CONFIG,
70};
71
72void mainboard_romstage_entry(unsigned long bist)
73{
74 struct pei_data pei_data = {
75 .pei_version = PEI_VERSION,
76 .mchbar = (uintptr_t)DEFAULT_MCHBAR,
77 .dmibar = (uintptr_t)DEFAULT_DMIBAR,
78 .epbar = DEFAULT_EPBAR,
79 .pciexbar = DEFAULT_PCIEXBAR,
80 .smbusbar = SMBUS_IO_BASE,
81 .wdbbar = 0x4000000,
82 .wdbsize = 0x1000,
83 .hpet_address = HPET_ADDR,
84 .rcba = (uintptr_t)DEFAULT_RCBA,
85 .pmbase = DEFAULT_PMBASE,
86 .gpiobase = DEFAULT_GPIOBASE,
87 .temp_mmio_base = 0xfed08000,
88 .system_type = 5, /* ULT */
89 .tseg_size = CONFIG_SMM_TSEG_SIZE,
90 .spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 },
91 .ec_present = 0,
92 // 0 = leave channel enabled
93 // 1 = disable dimm 0 on channel
94 // 2 = disable dimm 1 on channel
95 // 3 = disable dimm 0+1 on channel
96 .dimm_channel0_disabled = 2,
97 .dimm_channel1_disabled = 2,
98 // Enable 2x refresh mode
99 .ddr_refresh_2x = 1,
100 .dq_pins_interleaved = 1,
101 .max_ddr3_freq = 1600,
102 .usb_xhci_on_resume = 1,
103 .usb2_ports = {
104 /* Length, Enable, OCn#, Location */
105 { 0x0064, 1, 0, /* P0: VP8 */
106 USB_PORT_MINI_PCIE },
107 { 0x0040, 1, 0, /* P1: Port A, CN22 */
108 USB_PORT_INTERNAL },
109 { 0x0040, 1, 1, /* P2: Port B, CN23 */
110 USB_PORT_INTERNAL },
111 { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: WLAN */
112 USB_PORT_INTERNAL },
113 { 0x0040, 1, 2, /* P4: Port C, CN25 */
114 USB_PORT_INTERNAL },
115 { 0x0040, 1, 2, /* P5: Port D, CN25 */
116 USB_PORT_INTERNAL },
117 { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: Card Reader */
118 USB_PORT_INTERNAL },
119 { 0x0000, 0, 0, /* P7: N/C */
120 USB_PORT_SKIP },
121 },
122 .usb3_ports = {
123 /* Enable, OCn# */
124 { 1, 0 }, /* P1; CN22 */
125 { 1, 1 }, /* P2; CN23 */
126 { 1, 2 }, /* P3; CN25 */
127 { 1, 2 }, /* P4; CN25 */
128 },
129 };
130
131 struct romstage_params romstage_params = {
132 .pei_data = &pei_data,
133 .gpio_map = &mainboard_gpio_map,
134 .rcba_config = &rcba_config[0],
135 .bist = bist,
136 };
137
138 /* Early SuperIO setup */
139 ite_kill_watchdog(IT8772F_GPIO_DEV);
140 it8772f_ac_resume_southbridge(IT8772F_DUMMY_DEV);
141 pch_enable_lpc();
142 ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE);
143
144 /* Turn on Power LED */
145 set_power_led(LED_ON);
146
147 /* Call into the real romstage main with this board's attributes. */
148 romstage_common(&romstage_params);
149}