haswell boards: Correct USB config indentation
Change-Id: I72b717a41c5611cf578ce178722029b8646cbb35
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50539
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c
index f009f5a..dda2edc 100644
--- a/src/mainboard/google/beltino/romstage.c
+++ b/src/mainboard/google/beltino/romstage.c
@@ -46,30 +46,30 @@
spd_map[2] = 0xa4;
}
- const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
- /* Length, Enable, OCn#, Location */
- { 0x0064, 1, 0, /* P0: VP8 */
- USB_PORT_MINI_PCIE },
- { 0x0040, 1, 0, /* P1: Port A, CN22 */
- USB_PORT_INTERNAL },
- { 0x0040, 1, 1, /* P2: Port B, CN23 */
- USB_PORT_INTERNAL },
- { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: WLAN */
- USB_PORT_INTERNAL },
- { 0x0040, 1, 2, /* P4: Port C, CN25 */
- USB_PORT_INTERNAL },
- { 0x0040, 1, 2, /* P5: Port D, CN25 */
- USB_PORT_INTERNAL },
- { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: Card Reader */
- USB_PORT_INTERNAL },
- { 0x0000, 0, 0, /* P7: N/C */
- USB_PORT_SKIP },
- };
+const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+ /* Length, Enable, OCn#, Location */
+ { 0x0064, 1, 0, /* P0: VP8 */
+ USB_PORT_MINI_PCIE },
+ { 0x0040, 1, 0, /* P1: Port A, CN22 */
+ USB_PORT_INTERNAL },
+ { 0x0040, 1, 1, /* P2: Port B, CN23 */
+ USB_PORT_INTERNAL },
+ { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: WLAN */
+ USB_PORT_INTERNAL },
+ { 0x0040, 1, 2, /* P4: Port C, CN25 */
+ USB_PORT_INTERNAL },
+ { 0x0040, 1, 2, /* P5: Port D, CN25 */
+ USB_PORT_INTERNAL },
+ { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: Card Reader */
+ USB_PORT_INTERNAL },
+ { 0x0000, 0, 0, /* P7: N/C */
+ USB_PORT_SKIP },
+};
- const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
- /* Enable, OCn# */
- { 1, 0 }, /* P1; CN22 */
- { 1, 1 }, /* P2; CN23 */
- { 1, 2 }, /* P3; CN25 */
- { 1, 2 }, /* P4; CN25 */
- };
+const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+ /* Enable, OCn# */
+ { 1, 0 }, /* P1; CN22 */
+ { 1, 1 }, /* P2; CN23 */
+ { 1, 2 }, /* P3; CN25 */
+ { 1, 2 }, /* P4; CN25 */
+};