Angel Pons | 64b5d97 | 2020-04-05 13:20:50 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Matt DeVillier | 81ae67a | 2016-11-08 15:04:30 -0600 | [diff] [blame] | 3 | |
Matt DeVillier | 81ae67a | 2016-11-08 15:04:30 -0600 | [diff] [blame] | 4 | #include <stdint.h> |
Kyösti Mälkki | cd7a70f | 2019-08-17 20:51:08 +0300 | [diff] [blame] | 5 | #include <arch/romstage.h> |
Matt DeVillier | 81ae67a | 2016-11-08 15:04:30 -0600 | [diff] [blame] | 6 | #include <cpu/intel/haswell/haswell.h> |
| 7 | #include <northbridge/intel/haswell/haswell.h> |
| 8 | #include <northbridge/intel/haswell/raminit.h> |
| 9 | #include <southbridge/intel/lynxpoint/lp_gpio.h> |
| 10 | #include <southbridge/intel/lynxpoint/pch.h> |
| 11 | #include <superio/ite/common/ite.h> |
| 12 | #include <superio/ite/it8772f/it8772f.h> |
| 13 | #include <variant/gpio.h> |
| 14 | #include "onboard.h" |
| 15 | |
| 16 | const struct rcba_config_instruction rcba_config[] = { |
| 17 | |
| 18 | /* |
| 19 | * GFX INTA -> PIRQA (MSI) |
| 20 | * D28IP_P1IP PCIE INTA -> PIRQA |
| 21 | * D29IP_E1P EHCI INTA -> PIRQD |
| 22 | * D20IP_XHCI XHCI INTA -> PIRQC (MSI) |
| 23 | * D31IP_SIP SATA INTA -> PIRQF (MSI) |
| 24 | * D31IP_SMIP SMBUS INTB -> PIRQG |
| 25 | * D31IP_TTIP THRT INTC -> PIRQA |
| 26 | * D27IP_ZIP HDA INTA -> PIRQG (MSI) |
| 27 | */ |
| 28 | |
| 29 | /* Device interrupt pin register (board specific) */ |
| 30 | RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | |
| 31 | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), |
| 32 | RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), |
| 33 | RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | |
| 34 | (INTB << D28IP_P4IP)), |
| 35 | RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), |
| 36 | RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), |
| 37 | RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), |
| 38 | RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)), |
| 39 | |
| 40 | /* Device interrupt route registers */ |
| 41 | RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */ |
| 42 | RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */ |
| 43 | RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */ |
| 44 | RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */ |
| 45 | RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */ |
| 46 | RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */ |
| 47 | RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */ |
| 48 | RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */ |
| 49 | |
| 50 | /* Disable unused devices (board specific) */ |
| 51 | RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), |
| 52 | |
| 53 | RCBA_END_CONFIG, |
| 54 | }; |
| 55 | |
Kyösti Mälkki | 157b189 | 2019-08-16 14:02:25 +0300 | [diff] [blame] | 56 | void mainboard_romstage_entry(void) |
Matt DeVillier | 81ae67a | 2016-11-08 15:04:30 -0600 | [diff] [blame] | 57 | { |
| 58 | struct pei_data pei_data = { |
| 59 | .pei_version = PEI_VERSION, |
| 60 | .mchbar = (uintptr_t)DEFAULT_MCHBAR, |
| 61 | .dmibar = (uintptr_t)DEFAULT_DMIBAR, |
| 62 | .epbar = DEFAULT_EPBAR, |
Kyösti Mälkki | 503d324 | 2019-03-05 07:54:28 +0200 | [diff] [blame] | 63 | .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, |
Matt DeVillier | 81ae67a | 2016-11-08 15:04:30 -0600 | [diff] [blame] | 64 | .smbusbar = SMBUS_IO_BASE, |
| 65 | .wdbbar = 0x4000000, |
| 66 | .wdbsize = 0x1000, |
| 67 | .hpet_address = HPET_ADDR, |
| 68 | .rcba = (uintptr_t)DEFAULT_RCBA, |
| 69 | .pmbase = DEFAULT_PMBASE, |
| 70 | .gpiobase = DEFAULT_GPIOBASE, |
| 71 | .temp_mmio_base = 0xfed08000, |
| 72 | .system_type = 5, /* ULT */ |
| 73 | .tseg_size = CONFIG_SMM_TSEG_SIZE, |
| 74 | .spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 }, |
| 75 | .ec_present = 0, |
| 76 | // 0 = leave channel enabled |
| 77 | // 1 = disable dimm 0 on channel |
| 78 | // 2 = disable dimm 1 on channel |
| 79 | // 3 = disable dimm 0+1 on channel |
| 80 | .dimm_channel0_disabled = 2, |
| 81 | .dimm_channel1_disabled = 2, |
| 82 | // Enable 2x refresh mode |
| 83 | .ddr_refresh_2x = 1, |
| 84 | .dq_pins_interleaved = 1, |
| 85 | .max_ddr3_freq = 1600, |
| 86 | .usb_xhci_on_resume = 1, |
| 87 | .usb2_ports = { |
| 88 | /* Length, Enable, OCn#, Location */ |
| 89 | { 0x0064, 1, 0, /* P0: VP8 */ |
| 90 | USB_PORT_MINI_PCIE }, |
| 91 | { 0x0040, 1, 0, /* P1: Port A, CN22 */ |
| 92 | USB_PORT_INTERNAL }, |
| 93 | { 0x0040, 1, 1, /* P2: Port B, CN23 */ |
| 94 | USB_PORT_INTERNAL }, |
| 95 | { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: WLAN */ |
| 96 | USB_PORT_INTERNAL }, |
| 97 | { 0x0040, 1, 2, /* P4: Port C, CN25 */ |
| 98 | USB_PORT_INTERNAL }, |
| 99 | { 0x0040, 1, 2, /* P5: Port D, CN25 */ |
| 100 | USB_PORT_INTERNAL }, |
| 101 | { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: Card Reader */ |
| 102 | USB_PORT_INTERNAL }, |
| 103 | { 0x0000, 0, 0, /* P7: N/C */ |
| 104 | USB_PORT_SKIP }, |
| 105 | }, |
| 106 | .usb3_ports = { |
| 107 | /* Enable, OCn# */ |
| 108 | { 1, 0 }, /* P1; CN22 */ |
| 109 | { 1, 1 }, /* P2; CN23 */ |
| 110 | { 1, 2 }, /* P3; CN25 */ |
| 111 | { 1, 2 }, /* P4; CN25 */ |
| 112 | }, |
| 113 | }; |
| 114 | |
| 115 | struct romstage_params romstage_params = { |
| 116 | .pei_data = &pei_data, |
| 117 | .gpio_map = &mainboard_gpio_map, |
| 118 | .rcba_config = &rcba_config[0], |
Matt DeVillier | 81ae67a | 2016-11-08 15:04:30 -0600 | [diff] [blame] | 119 | }; |
| 120 | |
| 121 | /* Early SuperIO setup */ |
| 122 | ite_kill_watchdog(IT8772F_GPIO_DEV); |
Elyes HAOUAS | f5f1b38 | 2018-04-26 09:43:03 +0200 | [diff] [blame] | 123 | it8772f_ac_resume_southbridge(IT8772F_SUPERIO_DEV); |
Matt DeVillier | 81ae67a | 2016-11-08 15:04:30 -0600 | [diff] [blame] | 124 | pch_enable_lpc(); |
| 125 | ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE); |
| 126 | |
| 127 | /* Turn on Power LED */ |
| 128 | set_power_led(LED_ON); |
| 129 | |
| 130 | /* Call into the real romstage main with this board's attributes. */ |
| 131 | romstage_common(&romstage_params); |
| 132 | } |