Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 2 | |
| 3 | #include <amdblocks/chip.h> |
| 4 | #include <amdblocks/espi.h> |
| 5 | #include <amdblocks/lpc.h> |
| 6 | #include <arch/mmio.h> |
| 7 | #include <console/console.h> |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 8 | #include <espi.h> |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 9 | #include <soc/pci_devs.h> |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 10 | #include <timer.h> |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 11 | #include <types.h> |
| 12 | |
Furquan Shaikh | 98bc961 | 2020-05-09 19:31:55 -0700 | [diff] [blame] | 13 | static uintptr_t espi_bar; |
| 14 | |
| 15 | void espi_update_static_bar(uintptr_t bar) |
| 16 | { |
| 17 | espi_bar = bar; |
| 18 | } |
| 19 | |
Martin Roth | fe58977 | 2021-06-25 15:09:43 -0600 | [diff] [blame] | 20 | __weak void mb_set_up_early_espi(void) |
| 21 | { |
| 22 | } |
| 23 | |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 24 | static uintptr_t espi_get_bar(void) |
| 25 | { |
Martin Roth | b39e10d | 2020-07-14 11:08:55 -0600 | [diff] [blame] | 26 | if (ENV_X86 && !espi_bar) |
| 27 | espi_update_static_bar(lpc_get_spibase() + ESPI_OFFSET_FROM_BAR); |
Furquan Shaikh | 98bc961 | 2020-05-09 19:31:55 -0700 | [diff] [blame] | 28 | return espi_bar; |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 29 | } |
| 30 | |
Felix Held | 92dd678 | 2020-08-10 20:27:58 +0200 | [diff] [blame] | 31 | static uint32_t espi_read32(unsigned int reg) |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 32 | { |
| 33 | return read32((void *)(espi_get_bar() + reg)); |
| 34 | } |
| 35 | |
Felix Held | 92dd678 | 2020-08-10 20:27:58 +0200 | [diff] [blame] | 36 | static void espi_write32(unsigned int reg, uint32_t val) |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 37 | { |
| 38 | write32((void *)(espi_get_bar() + reg), val); |
| 39 | } |
| 40 | |
Felix Held | 92dd678 | 2020-08-10 20:27:58 +0200 | [diff] [blame] | 41 | static uint16_t espi_read16(unsigned int reg) |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 42 | { |
| 43 | return read16((void *)(espi_get_bar() + reg)); |
| 44 | } |
| 45 | |
Felix Held | 92dd678 | 2020-08-10 20:27:58 +0200 | [diff] [blame] | 46 | static void espi_write16(unsigned int reg, uint16_t val) |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 47 | { |
| 48 | write16((void *)(espi_get_bar() + reg), val); |
| 49 | } |
| 50 | |
Felix Held | 92dd678 | 2020-08-10 20:27:58 +0200 | [diff] [blame] | 51 | static uint8_t espi_read8(unsigned int reg) |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 52 | { |
| 53 | return read8((void *)(espi_get_bar() + reg)); |
| 54 | } |
| 55 | |
Felix Held | 92dd678 | 2020-08-10 20:27:58 +0200 | [diff] [blame] | 56 | static void espi_write8(unsigned int reg, uint8_t val) |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 57 | { |
| 58 | write8((void *)(espi_get_bar() + reg), val); |
| 59 | } |
| 60 | |
Felix Held | f08fbf8 | 2020-08-10 20:30:36 +0200 | [diff] [blame] | 61 | static void espi_enable_decode(uint32_t decode_en) |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 62 | { |
| 63 | uint32_t val; |
| 64 | |
| 65 | val = espi_read32(ESPI_DECODE); |
| 66 | val |= decode_en; |
| 67 | espi_write32(ESPI_DECODE, val); |
| 68 | } |
| 69 | |
Felix Held | f08fbf8 | 2020-08-10 20:30:36 +0200 | [diff] [blame] | 70 | static bool espi_is_decode_enabled(uint32_t decode) |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 71 | { |
| 72 | uint32_t val; |
| 73 | |
| 74 | val = espi_read32(ESPI_DECODE); |
| 75 | return !!(val & decode); |
| 76 | } |
| 77 | |
| 78 | static int espi_find_io_window(uint16_t win_base) |
| 79 | { |
| 80 | int i; |
| 81 | |
| 82 | for (i = 0; i < ESPI_GENERIC_IO_WIN_COUNT; i++) { |
| 83 | if (!espi_is_decode_enabled(ESPI_DECODE_IO_RANGE_EN(i))) |
| 84 | continue; |
| 85 | |
| 86 | if (espi_read16(ESPI_IO_RANGE_BASE(i)) == win_base) |
| 87 | return i; |
| 88 | } |
| 89 | |
| 90 | return -1; |
| 91 | } |
| 92 | |
| 93 | static int espi_get_unused_io_window(void) |
| 94 | { |
| 95 | int i; |
| 96 | |
| 97 | for (i = 0; i < ESPI_GENERIC_IO_WIN_COUNT; i++) { |
| 98 | if (!espi_is_decode_enabled(ESPI_DECODE_IO_RANGE_EN(i))) |
| 99 | return i; |
| 100 | } |
| 101 | |
| 102 | return -1; |
| 103 | } |
| 104 | |
Raul E Rangel | b95f848 | 2021-04-02 13:47:09 -0600 | [diff] [blame] | 105 | static void espi_clear_decodes(void) |
Martin Roth | 011bf13 | 2021-03-23 13:20:42 -0600 | [diff] [blame] | 106 | { |
| 107 | unsigned int idx; |
| 108 | |
| 109 | /* First turn off all enable bits, then zero base, range, and size registers */ |
Raul E Rangel | 01792e3 | 2021-04-26 13:52:38 -0600 | [diff] [blame] | 110 | espi_write16(ESPI_DECODE, 0); |
Martin Roth | 011bf13 | 2021-03-23 13:20:42 -0600 | [diff] [blame] | 111 | |
| 112 | for (idx = 0; idx < ESPI_GENERIC_IO_WIN_COUNT; idx++) { |
| 113 | espi_write16(ESPI_IO_RANGE_BASE(idx), 0); |
| 114 | espi_write8(ESPI_IO_RANGE_SIZE(idx), 0); |
| 115 | } |
| 116 | for (idx = 0; idx < ESPI_GENERIC_MMIO_WIN_COUNT; idx++) { |
| 117 | espi_write32(ESPI_MMIO_RANGE_BASE(idx), 0); |
| 118 | espi_write16(ESPI_MMIO_RANGE_SIZE(idx), 0); |
| 119 | } |
| 120 | } |
| 121 | |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 122 | /* |
| 123 | * Returns decode enable bits for standard IO port addresses. If port address is not supported |
| 124 | * by standard decode or if the size of window is not 1, then it returns -1. |
| 125 | */ |
| 126 | static int espi_std_io_decode(uint16_t base, size_t size) |
| 127 | { |
Felix Held | c0d4eeb | 2020-08-10 20:37:16 +0200 | [diff] [blame] | 128 | if (size == 2 && base == 0x2e) |
| 129 | return ESPI_DECODE_IO_0X2E_0X2F_EN; |
| 130 | |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 131 | if (size != 1) |
Felix Held | 4bf419f | 2020-08-10 20:33:25 +0200 | [diff] [blame] | 132 | return -1; |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 133 | |
| 134 | switch (base) { |
| 135 | case 0x80: |
Felix Held | 4bf419f | 2020-08-10 20:33:25 +0200 | [diff] [blame] | 136 | return ESPI_DECODE_IO_0x80_EN; |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 137 | case 0x60: |
| 138 | case 0x64: |
Felix Held | 4bf419f | 2020-08-10 20:33:25 +0200 | [diff] [blame] | 139 | return ESPI_DECODE_IO_0X60_0X64_EN; |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 140 | case 0x2e: |
| 141 | case 0x2f: |
Felix Held | 4bf419f | 2020-08-10 20:33:25 +0200 | [diff] [blame] | 142 | return ESPI_DECODE_IO_0X2E_0X2F_EN; |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 143 | default: |
Felix Held | 4bf419f | 2020-08-10 20:33:25 +0200 | [diff] [blame] | 144 | return -1; |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 145 | } |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 146 | } |
| 147 | |
| 148 | static size_t espi_get_io_window_size(int idx) |
| 149 | { |
| 150 | return espi_read8(ESPI_IO_RANGE_SIZE(idx)) + 1; |
| 151 | } |
| 152 | |
| 153 | static void espi_write_io_window(int idx, uint16_t base, size_t size) |
| 154 | { |
| 155 | espi_write16(ESPI_IO_RANGE_BASE(idx), base); |
| 156 | espi_write8(ESPI_IO_RANGE_SIZE(idx), size - 1); |
| 157 | } |
| 158 | |
| 159 | static int espi_open_generic_io_window(uint16_t base, size_t size) |
| 160 | { |
| 161 | size_t win_size; |
| 162 | int idx; |
| 163 | |
| 164 | for (; size; size -= win_size, base += win_size) { |
| 165 | win_size = MIN(size, ESPI_GENERIC_IO_MAX_WIN_SIZE); |
| 166 | |
| 167 | idx = espi_find_io_window(base); |
| 168 | if (idx != -1) { |
| 169 | size_t curr_size = espi_get_io_window_size(idx); |
| 170 | |
| 171 | if (curr_size > win_size) { |
| 172 | printk(BIOS_INFO, "eSPI window already configured to be larger than requested! "); |
| 173 | printk(BIOS_INFO, "Base: 0x%x, Requested size: 0x%zx, Actual size: 0x%zx\n", |
| 174 | base, win_size, curr_size); |
| 175 | } else if (curr_size < win_size) { |
| 176 | espi_write_io_window(idx, base, win_size); |
| 177 | printk(BIOS_INFO, "eSPI window at base: 0x%x resized from 0x%zx to 0x%zx\n", |
| 178 | base, curr_size, win_size); |
| 179 | } |
| 180 | |
| 181 | continue; |
| 182 | } |
| 183 | |
| 184 | idx = espi_get_unused_io_window(); |
| 185 | if (idx == -1) { |
| 186 | printk(BIOS_ERR, "Cannot open IO window base %x size %zx\n", base, |
| 187 | size); |
| 188 | printk(BIOS_ERR, "ERROR: No more available IO windows!\n"); |
| 189 | return -1; |
| 190 | } |
| 191 | |
| 192 | espi_write_io_window(idx, base, win_size); |
| 193 | espi_enable_decode(ESPI_DECODE_IO_RANGE_EN(idx)); |
| 194 | } |
| 195 | |
| 196 | return 0; |
| 197 | } |
| 198 | |
| 199 | int espi_open_io_window(uint16_t base, size_t size) |
| 200 | { |
| 201 | int std_io; |
| 202 | |
| 203 | std_io = espi_std_io_decode(base, size); |
| 204 | if (std_io != -1) { |
| 205 | espi_enable_decode(std_io); |
| 206 | return 0; |
Felix Held | b026c7c | 2020-08-10 20:43:53 +0200 | [diff] [blame] | 207 | } else { |
| 208 | return espi_open_generic_io_window(base, size); |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 209 | } |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 210 | } |
| 211 | |
| 212 | static int espi_find_mmio_window(uint32_t win_base) |
| 213 | { |
| 214 | int i; |
| 215 | |
| 216 | for (i = 0; i < ESPI_GENERIC_MMIO_WIN_COUNT; i++) { |
| 217 | if (!espi_is_decode_enabled(ESPI_DECODE_MMIO_RANGE_EN(i))) |
| 218 | continue; |
| 219 | |
| 220 | if (espi_read32(ESPI_MMIO_RANGE_BASE(i)) == win_base) |
| 221 | return i; |
| 222 | } |
| 223 | |
| 224 | return -1; |
| 225 | } |
| 226 | |
| 227 | static int espi_get_unused_mmio_window(void) |
| 228 | { |
| 229 | int i; |
| 230 | |
| 231 | for (i = 0; i < ESPI_GENERIC_MMIO_WIN_COUNT; i++) { |
| 232 | if (!espi_is_decode_enabled(ESPI_DECODE_MMIO_RANGE_EN(i))) |
| 233 | return i; |
| 234 | } |
| 235 | |
| 236 | return -1; |
| 237 | |
| 238 | } |
| 239 | |
| 240 | static size_t espi_get_mmio_window_size(int idx) |
| 241 | { |
| 242 | return espi_read16(ESPI_MMIO_RANGE_SIZE(idx)) + 1; |
| 243 | } |
| 244 | |
| 245 | static void espi_write_mmio_window(int idx, uint32_t base, size_t size) |
| 246 | { |
| 247 | espi_write32(ESPI_MMIO_RANGE_BASE(idx), base); |
| 248 | espi_write16(ESPI_MMIO_RANGE_SIZE(idx), size - 1); |
| 249 | } |
| 250 | |
| 251 | int espi_open_mmio_window(uint32_t base, size_t size) |
| 252 | { |
| 253 | size_t win_size; |
| 254 | int idx; |
| 255 | |
| 256 | for (; size; size -= win_size, base += win_size) { |
| 257 | win_size = MIN(size, ESPI_GENERIC_MMIO_MAX_WIN_SIZE); |
| 258 | |
| 259 | idx = espi_find_mmio_window(base); |
| 260 | if (idx != -1) { |
| 261 | size_t curr_size = espi_get_mmio_window_size(idx); |
| 262 | |
| 263 | if (curr_size > win_size) { |
| 264 | printk(BIOS_INFO, "eSPI window already configured to be larger than requested! "); |
| 265 | printk(BIOS_INFO, "Base: 0x%x, Requested size: 0x%zx, Actual size: 0x%zx\n", |
| 266 | base, win_size, curr_size); |
| 267 | } else if (curr_size < win_size) { |
| 268 | espi_write_mmio_window(idx, base, win_size); |
| 269 | printk(BIOS_INFO, "eSPI window at base: 0x%x resized from 0x%zx to 0x%zx\n", |
| 270 | base, curr_size, win_size); |
| 271 | } |
| 272 | |
| 273 | continue; |
| 274 | } |
| 275 | |
| 276 | idx = espi_get_unused_mmio_window(); |
| 277 | if (idx == -1) { |
| 278 | printk(BIOS_ERR, "Cannot open IO window base %x size %zx\n", base, |
| 279 | size); |
| 280 | printk(BIOS_ERR, "ERROR: No more available MMIO windows!\n"); |
| 281 | return -1; |
| 282 | } |
| 283 | |
| 284 | espi_write_mmio_window(idx, base, win_size); |
| 285 | espi_enable_decode(ESPI_DECODE_MMIO_RANGE_EN(idx)); |
| 286 | } |
| 287 | |
| 288 | return 0; |
| 289 | } |
| 290 | |
| 291 | static const struct espi_config *espi_get_config(void) |
| 292 | { |
| 293 | const struct soc_amd_common_config *soc_cfg = soc_get_common_config(); |
| 294 | |
| 295 | if (!soc_cfg) |
| 296 | die("Common config structure is NULL!\n"); |
| 297 | |
| 298 | return &soc_cfg->espi_config; |
| 299 | } |
| 300 | |
Raul E Rangel | 61ac1bc | 2021-04-02 10:55:27 -0600 | [diff] [blame] | 301 | static int espi_configure_decodes(const struct espi_config *cfg) |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 302 | { |
Felix Held | 9e83054 | 2021-12-18 00:41:23 +0100 | [diff] [blame^] | 303 | int i; |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 304 | |
| 305 | espi_enable_decode(cfg->std_io_decode_bitmap); |
| 306 | |
| 307 | for (i = 0; i < ESPI_GENERIC_IO_WIN_COUNT; i++) { |
| 308 | if (cfg->generic_io_range[i].size == 0) |
| 309 | continue; |
Felix Held | 9e83054 | 2021-12-18 00:41:23 +0100 | [diff] [blame^] | 310 | if (espi_open_generic_io_window(cfg->generic_io_range[i].base, |
| 311 | cfg->generic_io_range[i].size)) |
| 312 | return -1; |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 313 | } |
Raul E Rangel | 61ac1bc | 2021-04-02 10:55:27 -0600 | [diff] [blame] | 314 | |
| 315 | return 0; |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 316 | } |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 317 | |
| 318 | #define ESPI_DN_TX_HDR0 0x00 |
| 319 | enum espi_cmd_type { |
| 320 | CMD_TYPE_SET_CONFIGURATION = 0, |
| 321 | CMD_TYPE_GET_CONFIGURATION = 1, |
| 322 | CMD_TYPE_IN_BAND_RESET = 2, |
| 323 | CMD_TYPE_PERIPHERAL = 4, |
| 324 | CMD_TYPE_VW = 5, |
| 325 | CMD_TYPE_OOB = 6, |
| 326 | CMD_TYPE_FLASH = 7, |
| 327 | }; |
| 328 | |
| 329 | #define ESPI_DN_TX_HDR1 0x04 |
| 330 | #define ESPI_DN_TX_HDR2 0x08 |
| 331 | #define ESPI_DN_TX_DATA 0x0c |
| 332 | |
| 333 | #define ESPI_MASTER_CAP 0x2c |
| 334 | #define ESPI_VW_MAX_SIZE_SHIFT 13 |
| 335 | #define ESPI_VW_MAX_SIZE_MASK (0x3f << ESPI_VW_MAX_SIZE_SHIFT) |
| 336 | |
Raul E Rangel | 1d0e493 | 2021-04-02 10:27:11 -0600 | [diff] [blame] | 337 | #define ESPI_GLOBAL_CONTROL_0 0x30 |
| 338 | #define ESPI_WAIT_CNT_SHIFT 24 |
| 339 | #define ESPI_WAIT_CNT_MASK (0x3F << ESPI_WAIT_CNT_SHIFT) |
| 340 | #define ESPI_WDG_CNT_SHIFT 8 |
| 341 | #define ESPI_WDG_CNT_MASK (0xFFFF << ESPI_WDG_CNT_SHIFT) |
| 342 | #define ESPI_AL_IDLE_TIMER_SHIFT 4 |
| 343 | #define ESPI_AL_IDLE_TIMER_MASK (0x7 << ESPI_AL_IDLE_TIMER_SHIFT) |
| 344 | #define ESPI_AL_STOP_EN (1 << 3) |
| 345 | #define ESPI_PR_CLKGAT_EN (1 << 2) |
| 346 | #define ESPI_WAIT_CHKEN (1 << 1) |
| 347 | #define ESPI_WDG_EN (1 << 0) |
| 348 | |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 349 | #define ESPI_GLOBAL_CONTROL_1 0x34 |
Raul E Rangel | 1d0e493 | 2021-04-02 10:27:11 -0600 | [diff] [blame] | 350 | #define ESPI_RGCMD_INT_MAP_SHIFT 13 |
| 351 | #define ESPI_RGCMD_INT_MAP_MASK (0x1F << ESPI_RGCMD_INT_MAP_SHIFT) |
| 352 | #define ESPI_RGCMD_INT(irq) ((irq) << ESPI_RGCMD_INT_MAP_SHIFT) |
| 353 | #define ESPI_RGCMD_INT_SMI (0x1F << ESPI_RGCMD_INT_MAP_SHIFT) |
| 354 | #define ESPI_ERR_INT_MAP_SHIFT 8 |
| 355 | #define ESPI_ERR_INT_MAP_MASK (0x1F << ESPI_ERR_INT_MAP_SHIFT) |
| 356 | #define ESPI_ERR_INT(irq) ((irq) << ESPI_ERR_INT_MAP_SHIFT) |
| 357 | #define ESPI_ERR_INT_SMI (0x1F << ESPI_ERR_INT_MAP_SHIFT) |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 358 | #define ESPI_SUB_DECODE_SLV_SHIFT 3 |
| 359 | #define ESPI_SUB_DECODE_SLV_MASK (0x3 << ESPI_SUB_DECODE_SLV_SHIFT) |
| 360 | #define ESPI_SUB_DECODE_EN (1 << 2) |
Raul E Rangel | 1d0e493 | 2021-04-02 10:27:11 -0600 | [diff] [blame] | 361 | #define ESPI_BUS_MASTER_EN (1 << 1) |
| 362 | #define ESPI_SW_RST (1 << 0) |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 363 | |
Raul E Rangel | 1d0e493 | 2021-04-02 10:27:11 -0600 | [diff] [blame] | 364 | #define ESPI_SLAVE0_INT_EN 0x6C |
Raul E Rangel | 4774012 | 2021-04-02 10:16:54 -0600 | [diff] [blame] | 365 | #define ESPI_SLAVE0_INT_STS 0x70 |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 366 | #define ESPI_STATUS_DNCMD_COMPLETE (1 << 28) |
| 367 | #define ESPI_STATUS_NON_FATAL_ERROR (1 << 6) |
| 368 | #define ESPI_STATUS_FATAL_ERROR (1 << 5) |
| 369 | #define ESPI_STATUS_NO_RESPONSE (1 << 4) |
| 370 | #define ESPI_STATUS_CRC_ERR (1 << 2) |
| 371 | #define ESPI_STATUS_WAIT_TIMEOUT (1 << 1) |
| 372 | #define ESPI_STATUS_BUS_ERROR (1 << 0) |
| 373 | |
| 374 | #define ESPI_RXVW_POLARITY 0xac |
| 375 | |
| 376 | #define ESPI_CMD_TIMEOUT_US 100 |
Raul E Rangel | 0318dc1 | 2021-05-21 16:31:52 -0600 | [diff] [blame] | 377 | #define ESPI_CH_READY_TIMEOUT_US 10000 |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 378 | |
| 379 | union espi_txhdr0 { |
| 380 | uint32_t val; |
| 381 | struct { |
| 382 | uint32_t cmd_type:3; |
| 383 | uint32_t cmd_sts:1; |
| 384 | uint32_t slave_sel:2; |
| 385 | uint32_t rsvd:2; |
| 386 | uint32_t hdata0:8; |
| 387 | uint32_t hdata1:8; |
| 388 | uint32_t hdata2:8; |
| 389 | }; |
| 390 | } __packed; |
| 391 | |
| 392 | union espi_txhdr1 { |
| 393 | uint32_t val; |
| 394 | struct { |
| 395 | uint32_t hdata3:8; |
| 396 | uint32_t hdata4:8; |
| 397 | uint32_t hdata5:8; |
| 398 | uint32_t hdata6:8; |
| 399 | }; |
| 400 | } __packed; |
| 401 | |
| 402 | union espi_txhdr2 { |
| 403 | uint32_t val; |
| 404 | struct { |
| 405 | uint32_t hdata7:8; |
| 406 | uint32_t rsvd:24; |
| 407 | }; |
| 408 | } __packed; |
| 409 | |
| 410 | union espi_txdata { |
| 411 | uint32_t val; |
| 412 | struct { |
| 413 | uint32_t byte0:8; |
| 414 | uint32_t byte1:8; |
| 415 | uint32_t byte2:8; |
| 416 | uint32_t byte3:8; |
| 417 | }; |
| 418 | } __packed; |
| 419 | |
| 420 | struct espi_cmd { |
| 421 | union espi_txhdr0 hdr0; |
| 422 | union espi_txhdr1 hdr1; |
| 423 | union espi_txhdr2 hdr2; |
| 424 | union espi_txdata data; |
Raul E Rangel | 12c0542 | 2021-05-11 11:13:38 -0600 | [diff] [blame] | 425 | uint32_t expected_status_codes; |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 426 | } __packed; |
| 427 | |
| 428 | /* Wait up to ESPI_CMD_TIMEOUT_US for hardware to clear DNCMD_STATUS bit. */ |
| 429 | static int espi_wait_ready(void) |
| 430 | { |
| 431 | struct stopwatch sw; |
| 432 | union espi_txhdr0 hdr0; |
| 433 | |
| 434 | stopwatch_init_usecs_expire(&sw, ESPI_CMD_TIMEOUT_US); |
| 435 | do { |
| 436 | hdr0.val = espi_read32(ESPI_DN_TX_HDR0); |
| 437 | if (!hdr0.cmd_sts) |
| 438 | return 0; |
| 439 | } while (!stopwatch_expired(&sw)); |
| 440 | |
| 441 | return -1; |
| 442 | } |
| 443 | |
| 444 | /* Clear interrupt status register */ |
| 445 | static void espi_clear_status(void) |
| 446 | { |
Raul E Rangel | 4774012 | 2021-04-02 10:16:54 -0600 | [diff] [blame] | 447 | uint32_t status = espi_read32(ESPI_SLAVE0_INT_STS); |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 448 | if (status) |
Raul E Rangel | 4774012 | 2021-04-02 10:16:54 -0600 | [diff] [blame] | 449 | espi_write32(ESPI_SLAVE0_INT_STS, status); |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 450 | } |
| 451 | |
| 452 | /* |
| 453 | * Wait up to ESPI_CMD_TIMEOUT_US for interrupt status register to update after sending a |
| 454 | * command. |
| 455 | */ |
Felix Held | 1ba3833 | 2020-08-10 20:45:30 +0200 | [diff] [blame] | 456 | static int espi_poll_status(uint32_t *status) |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 457 | { |
| 458 | struct stopwatch sw; |
| 459 | |
| 460 | stopwatch_init_usecs_expire(&sw, ESPI_CMD_TIMEOUT_US); |
| 461 | do { |
Raul E Rangel | 4774012 | 2021-04-02 10:16:54 -0600 | [diff] [blame] | 462 | *status = espi_read32(ESPI_SLAVE0_INT_STS); |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 463 | if (*status) |
| 464 | return 0; |
| 465 | } while (!stopwatch_expired(&sw)); |
| 466 | |
| 467 | printk(BIOS_ERR, "Error: eSPI timed out waiting for status update.\n"); |
| 468 | |
| 469 | return -1; |
| 470 | } |
| 471 | |
| 472 | static void espi_show_failure(const struct espi_cmd *cmd, const char *str, uint32_t status) |
| 473 | { |
| 474 | printk(BIOS_ERR, "eSPI cmd0-cmd2: %08x %08x %08x data: %08x.\n", |
| 475 | cmd->hdr0.val, cmd->hdr1.val, cmd->hdr2.val, cmd->data.val); |
| 476 | printk(BIOS_ERR, "%s (Status = 0x%x)\n", str, status); |
| 477 | } |
| 478 | |
| 479 | static int espi_send_command(const struct espi_cmd *cmd) |
| 480 | { |
| 481 | uint32_t status; |
| 482 | |
| 483 | if (CONFIG(ESPI_DEBUG)) |
Raul E Rangel | f702705 | 2021-06-29 13:12:19 -0600 | [diff] [blame] | 484 | printk(BIOS_DEBUG, "eSPI cmd0-cmd2: %08x %08x %08x data: %08x.\n", |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 485 | cmd->hdr0.val, cmd->hdr1.val, cmd->hdr2.val, cmd->data.val); |
| 486 | |
| 487 | if (espi_wait_ready() == -1) { |
| 488 | espi_show_failure(cmd, "Error: eSPI was not ready to accept a command", 0); |
| 489 | return -1; |
| 490 | } |
| 491 | |
| 492 | espi_clear_status(); |
| 493 | |
| 494 | espi_write32(ESPI_DN_TX_HDR1, cmd->hdr1.val); |
| 495 | espi_write32(ESPI_DN_TX_HDR2, cmd->hdr2.val); |
| 496 | espi_write32(ESPI_DN_TX_DATA, cmd->data.val); |
| 497 | |
| 498 | /* Dword 0 must be last as this write triggers the transaction */ |
| 499 | espi_write32(ESPI_DN_TX_HDR0, cmd->hdr0.val); |
| 500 | |
| 501 | if (espi_wait_ready() == -1) { |
| 502 | espi_show_failure(cmd, |
| 503 | "Error: eSPI timed out waiting for command to complete", 0); |
| 504 | return -1; |
| 505 | } |
| 506 | |
Felix Held | 1ba3833 | 2020-08-10 20:45:30 +0200 | [diff] [blame] | 507 | if (espi_poll_status(&status) == -1) { |
| 508 | espi_show_failure(cmd, "Error: eSPI poll status failed", 0); |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 509 | return -1; |
| 510 | } |
| 511 | |
| 512 | /* If command did not complete downstream, return error. */ |
| 513 | if (!(status & ESPI_STATUS_DNCMD_COMPLETE)) { |
| 514 | espi_show_failure(cmd, "Error: eSPI downstream command completion failure", |
| 515 | status); |
| 516 | return -1; |
| 517 | } |
| 518 | |
Raul E Rangel | 12c0542 | 2021-05-11 11:13:38 -0600 | [diff] [blame] | 519 | if (status & ~(ESPI_STATUS_DNCMD_COMPLETE | cmd->expected_status_codes)) { |
Felix Held | 316d59c | 2020-08-10 20:42:20 +0200 | [diff] [blame] | 520 | espi_show_failure(cmd, "Error: unexpected eSPI status register bits set", |
| 521 | status); |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 522 | return -1; |
| 523 | } |
| 524 | |
Raul E Rangel | 12c0542 | 2021-05-11 11:13:38 -0600 | [diff] [blame] | 525 | espi_write32(ESPI_SLAVE0_INT_STS, status); |
Raul E Rangel | 66c52ff | 2021-04-02 10:18:25 -0600 | [diff] [blame] | 526 | |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 527 | return 0; |
| 528 | } |
| 529 | |
| 530 | static int espi_send_reset(void) |
| 531 | { |
| 532 | struct espi_cmd cmd = { |
| 533 | .hdr0 = { |
| 534 | .cmd_type = CMD_TYPE_IN_BAND_RESET, |
| 535 | .cmd_sts = 1, |
| 536 | }, |
Raul E Rangel | 12c0542 | 2021-05-11 11:13:38 -0600 | [diff] [blame] | 537 | |
| 538 | /* |
| 539 | * When performing an in-band reset the host controller and the |
| 540 | * peripheral can have mismatched IO configs. |
| 541 | * |
| 542 | * i.e., The eSPI peripheral can be in IO-4 mode while, the |
| 543 | * eSPI host will be in IO-1. This results in the peripheral |
| 544 | * getting invalid packets and thus not responding. |
| 545 | * |
| 546 | * If the peripheral is alerting when we perform an in-band |
| 547 | * reset, there is a race condition in espi_send_command. |
| 548 | * 1) espi_send_command clears the interrupt status. |
| 549 | * 2) eSPI host controller hardware notices the alert and sends |
| 550 | * a GET_STATUS. |
| 551 | * 3) espi_send_command writes the in-band reset command. |
| 552 | * 4) eSPI hardware enqueues the in-band reset until GET_STATUS |
| 553 | * is complete. |
| 554 | * 5) GET_STATUS fails with NO_RESPONSE and sets the interrupt |
| 555 | * status. |
| 556 | * 6) eSPI hardware performs in-band reset. |
| 557 | * 7) espi_send_command checks the status and sees a |
| 558 | * NO_RESPONSE bit. |
| 559 | * |
| 560 | * As a workaround we allow the NO_RESPONSE status code when |
| 561 | * we perform an in-band reset. |
| 562 | */ |
| 563 | .expected_status_codes = ESPI_STATUS_NO_RESPONSE, |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 564 | }; |
| 565 | |
| 566 | return espi_send_command(&cmd); |
| 567 | } |
| 568 | |
Raul E Rangel | 43aa527 | 2021-05-21 17:04:28 -0600 | [diff] [blame] | 569 | static int espi_send_pltrst(const struct espi_config *mb_cfg, bool assert) |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 570 | { |
| 571 | struct espi_cmd cmd = { |
| 572 | .hdr0 = { |
| 573 | .cmd_type = CMD_TYPE_VW, |
| 574 | .cmd_sts = 1, |
| 575 | .hdata0 = 0, /* 1 VW group */ |
| 576 | }, |
| 577 | .data = { |
| 578 | .byte0 = ESPI_VW_INDEX_SYSTEM_EVENT_3, |
Raul E Rangel | 43aa527 | 2021-05-21 17:04:28 -0600 | [diff] [blame] | 579 | .byte1 = assert ? ESPI_VW_SIGNAL_LOW(ESPI_VW_PLTRST) |
| 580 | : ESPI_VW_SIGNAL_HIGH(ESPI_VW_PLTRST), |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 581 | }, |
| 582 | }; |
| 583 | |
| 584 | if (!mb_cfg->vw_ch_en) |
| 585 | return 0; |
| 586 | |
| 587 | return espi_send_command(&cmd); |
| 588 | } |
| 589 | |
| 590 | /* |
| 591 | * In case of get configuration command, hdata0 contains bits 15:8 of the slave register address |
| 592 | * and hdata1 contains bits 7:0 of the slave register address. |
| 593 | */ |
| 594 | #define ESPI_CONFIGURATION_HDATA0(a) (((a) >> 8) & 0xff) |
| 595 | #define ESPI_CONFIGURATION_HDATA1(a) ((a) & 0xff) |
| 596 | |
| 597 | static int espi_get_configuration(uint16_t slave_reg_addr, uint32_t *config) |
| 598 | { |
| 599 | struct espi_cmd cmd = { |
| 600 | .hdr0 = { |
| 601 | .cmd_type = CMD_TYPE_GET_CONFIGURATION, |
| 602 | .cmd_sts = 1, |
| 603 | .hdata0 = ESPI_CONFIGURATION_HDATA0(slave_reg_addr), |
| 604 | .hdata1 = ESPI_CONFIGURATION_HDATA1(slave_reg_addr), |
| 605 | }, |
| 606 | }; |
| 607 | |
| 608 | *config = 0; |
| 609 | |
| 610 | if (espi_send_command(&cmd)) |
| 611 | return -1; |
| 612 | |
| 613 | *config = espi_read32(ESPI_DN_TX_HDR1); |
| 614 | |
| 615 | if (CONFIG(ESPI_DEBUG)) |
| 616 | printk(BIOS_DEBUG, "Get configuration for slave register(0x%x): 0x%x\n", |
| 617 | slave_reg_addr, *config); |
| 618 | |
| 619 | return 0; |
| 620 | } |
| 621 | |
| 622 | static int espi_set_configuration(uint16_t slave_reg_addr, uint32_t config) |
| 623 | { |
| 624 | struct espi_cmd cmd = { |
| 625 | .hdr0 = { |
| 626 | .cmd_type = CMD_TYPE_SET_CONFIGURATION, |
| 627 | .cmd_sts = 1, |
| 628 | .hdata0 = ESPI_CONFIGURATION_HDATA0(slave_reg_addr), |
| 629 | .hdata1 = ESPI_CONFIGURATION_HDATA1(slave_reg_addr), |
| 630 | }, |
| 631 | .hdr1 = { |
| 632 | .val = config, |
| 633 | }, |
| 634 | }; |
| 635 | |
| 636 | return espi_send_command(&cmd); |
| 637 | } |
| 638 | |
| 639 | static int espi_get_general_configuration(uint32_t *config) |
| 640 | { |
Felix Held | d992aa6 | 2021-12-18 00:41:23 +0100 | [diff] [blame] | 641 | if (espi_get_configuration(ESPI_SLAVE_GENERAL_CFG, config) == -1) |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 642 | return -1; |
| 643 | |
| 644 | espi_show_slave_general_configuration(*config); |
| 645 | return 0; |
| 646 | } |
| 647 | |
| 648 | static void espi_set_io_mode_config(enum espi_io_mode mb_io_mode, uint32_t slave_caps, |
| 649 | uint32_t *slave_config, uint32_t *ctrlr_config) |
| 650 | { |
| 651 | switch (mb_io_mode) { |
| 652 | case ESPI_IO_MODE_QUAD: |
| 653 | if (espi_slave_supports_quad_io(slave_caps)) { |
| 654 | *slave_config |= ESPI_SLAVE_IO_MODE_SEL_QUAD; |
| 655 | *ctrlr_config |= ESPI_IO_MODE_QUAD; |
| 656 | break; |
| 657 | } |
| 658 | printk(BIOS_ERR, "Error: eSPI Quad I/O not supported. Dropping to dual mode.\n"); |
| 659 | /* Intentional fall-through */ |
| 660 | case ESPI_IO_MODE_DUAL: |
| 661 | if (espi_slave_supports_dual_io(slave_caps)) { |
| 662 | *slave_config |= ESPI_SLAVE_IO_MODE_SEL_DUAL; |
| 663 | *ctrlr_config |= ESPI_IO_MODE_DUAL; |
| 664 | break; |
| 665 | } |
| 666 | printk(BIOS_ERR, |
| 667 | "Error: eSPI Dual I/O not supported. Dropping to single mode.\n"); |
| 668 | /* Intentional fall-through */ |
| 669 | case ESPI_IO_MODE_SINGLE: |
| 670 | /* Single I/O mode is always supported. */ |
| 671 | *slave_config |= ESPI_SLAVE_IO_MODE_SEL_SINGLE; |
| 672 | *ctrlr_config |= ESPI_IO_MODE_SINGLE; |
| 673 | break; |
| 674 | default: |
| 675 | die("No supported eSPI I/O modes!\n"); |
| 676 | } |
| 677 | } |
| 678 | |
| 679 | static void espi_set_op_freq_config(enum espi_op_freq mb_op_freq, uint32_t slave_caps, |
| 680 | uint32_t *slave_config, uint32_t *ctrlr_config) |
| 681 | { |
| 682 | int slave_max_speed_mhz = espi_slave_max_speed_mhz_supported(slave_caps); |
| 683 | |
| 684 | switch (mb_op_freq) { |
| 685 | case ESPI_OP_FREQ_66_MHZ: |
| 686 | if (slave_max_speed_mhz >= 66) { |
| 687 | *slave_config |= ESPI_SLAVE_OP_FREQ_SEL_66_MHZ; |
| 688 | *ctrlr_config |= ESPI_OP_FREQ_66_MHZ; |
| 689 | break; |
| 690 | } |
| 691 | printk(BIOS_ERR, "Error: eSPI 66MHz not supported. Dropping to 33MHz.\n"); |
| 692 | /* Intentional fall-through */ |
| 693 | case ESPI_OP_FREQ_33_MHZ: |
| 694 | if (slave_max_speed_mhz >= 33) { |
| 695 | *slave_config |= ESPI_SLAVE_OP_FREQ_SEL_33_MHZ; |
| 696 | *ctrlr_config |= ESPI_OP_FREQ_33_MHZ; |
| 697 | break; |
| 698 | } |
| 699 | printk(BIOS_ERR, "Error: eSPI 33MHz not supported. Dropping to 16MHz.\n"); |
| 700 | /* Intentional fall-through */ |
| 701 | case ESPI_OP_FREQ_16_MHZ: |
| 702 | /* |
| 703 | * eSPI spec says the minimum frequency is 20MHz, but AMD datasheets support |
| 704 | * 16.7 Mhz. |
| 705 | */ |
| 706 | if (slave_max_speed_mhz > 0) { |
| 707 | *slave_config |= ESPI_SLAVE_OP_FREQ_SEL_20_MHZ; |
| 708 | *ctrlr_config |= ESPI_OP_FREQ_16_MHZ; |
| 709 | break; |
| 710 | } |
| 711 | /* Intentional fall-through */ |
| 712 | default: |
| 713 | die("No supported eSPI Operating Frequency!\n"); |
| 714 | } |
| 715 | } |
| 716 | |
Raul E Rangel | 8317e72 | 2021-05-05 13:38:27 -0600 | [diff] [blame] | 717 | static void espi_set_alert_pin_config(enum espi_alert_pin alert_pin, uint32_t slave_caps, |
| 718 | uint32_t *slave_config, uint32_t *ctrlr_config) |
| 719 | { |
| 720 | switch (alert_pin) { |
| 721 | case ESPI_ALERT_PIN_IN_BAND: |
| 722 | *slave_config |= ESPI_SLAVE_ALERT_MODE_IO1; |
| 723 | return; |
| 724 | case ESPI_ALERT_PIN_PUSH_PULL: |
| 725 | *slave_config |= ESPI_SLAVE_ALERT_MODE_PIN | ESPI_SLAVE_PUSH_PULL_ALERT_SEL; |
| 726 | *ctrlr_config |= ESPI_ALERT_MODE; |
| 727 | return; |
| 728 | case ESPI_ALERT_PIN_OPEN_DRAIN: |
| 729 | if (!(slave_caps & ESPI_SLAVE_OPEN_DRAIN_ALERT_SUPP)) |
| 730 | die("eSPI peripheral does not support open drain alert!"); |
| 731 | |
| 732 | *slave_config |= ESPI_SLAVE_ALERT_MODE_PIN | ESPI_SLAVE_OPEN_DRAIN_ALERT_SEL; |
| 733 | *ctrlr_config |= ESPI_ALERT_MODE; |
| 734 | return; |
| 735 | default: |
| 736 | die("Unknown espi alert config: %u!\n", alert_pin); |
| 737 | } |
| 738 | } |
| 739 | |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 740 | static int espi_set_general_configuration(const struct espi_config *mb_cfg, uint32_t slave_caps) |
| 741 | { |
| 742 | uint32_t slave_config = 0; |
| 743 | uint32_t ctrlr_config = 0; |
| 744 | |
| 745 | if (mb_cfg->crc_check_enable) { |
| 746 | slave_config |= ESPI_SLAVE_CRC_ENABLE; |
| 747 | ctrlr_config |= ESPI_CRC_CHECKING_EN; |
| 748 | } |
| 749 | |
Raul E Rangel | 8317e72 | 2021-05-05 13:38:27 -0600 | [diff] [blame] | 750 | espi_set_alert_pin_config(mb_cfg->alert_pin, slave_caps, &slave_config, &ctrlr_config); |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 751 | espi_set_io_mode_config(mb_cfg->io_mode, slave_caps, &slave_config, &ctrlr_config); |
| 752 | espi_set_op_freq_config(mb_cfg->op_freq_mhz, slave_caps, &slave_config, &ctrlr_config); |
| 753 | |
| 754 | if (CONFIG(ESPI_DEBUG)) |
| 755 | printk(BIOS_INFO, "Setting general configuration: slave: 0x%x controller: 0x%x\n", |
| 756 | slave_config, ctrlr_config); |
| 757 | |
Raul E Rangel | d2d762a | 2021-05-05 13:30:10 -0600 | [diff] [blame] | 758 | espi_show_slave_general_configuration(slave_config); |
| 759 | |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 760 | if (espi_set_configuration(ESPI_SLAVE_GENERAL_CFG, slave_config) == -1) |
| 761 | return -1; |
| 762 | |
| 763 | espi_write32(ESPI_SLAVE0_CONFIG, ctrlr_config); |
| 764 | return 0; |
| 765 | } |
| 766 | |
| 767 | static int espi_wait_channel_ready(uint16_t slave_reg_addr) |
| 768 | { |
| 769 | struct stopwatch sw; |
| 770 | uint32_t config; |
| 771 | |
| 772 | stopwatch_init_usecs_expire(&sw, ESPI_CH_READY_TIMEOUT_US); |
| 773 | do { |
| 774 | espi_get_configuration(slave_reg_addr, &config); |
| 775 | if (espi_slave_is_channel_ready(config)) |
| 776 | return 0; |
| 777 | } while (!stopwatch_expired(&sw)); |
| 778 | |
| 779 | printk(BIOS_ERR, "Error: Channel is not ready after %d usec (slave addr: 0x%x)\n", |
| 780 | ESPI_CH_READY_TIMEOUT_US, slave_reg_addr); |
| 781 | return -1; |
| 782 | |
| 783 | } |
| 784 | |
| 785 | static void espi_enable_ctrlr_channel(uint32_t channel_en) |
| 786 | { |
| 787 | uint32_t reg = espi_read32(ESPI_SLAVE0_CONFIG); |
| 788 | |
| 789 | reg |= channel_en; |
| 790 | |
| 791 | espi_write32(ESPI_SLAVE0_CONFIG, reg); |
| 792 | } |
| 793 | |
| 794 | static int espi_set_channel_configuration(uint32_t slave_config, uint32_t slave_reg_addr, |
| 795 | uint32_t ctrlr_enable) |
| 796 | { |
| 797 | if (espi_set_configuration(slave_reg_addr, slave_config) == -1) |
| 798 | return -1; |
| 799 | |
| 800 | if (!(slave_config & ESPI_SLAVE_CHANNEL_ENABLE)) |
| 801 | return 0; |
| 802 | |
| 803 | if (espi_wait_channel_ready(slave_reg_addr) == -1) |
| 804 | return -1; |
| 805 | |
| 806 | espi_enable_ctrlr_channel(ctrlr_enable); |
| 807 | return 0; |
| 808 | } |
| 809 | |
| 810 | static int espi_setup_vw_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) |
| 811 | { |
| 812 | uint32_t slave_vw_caps; |
| 813 | uint32_t ctrlr_vw_caps; |
| 814 | uint32_t slave_vw_count_supp; |
| 815 | uint32_t ctrlr_vw_count_supp; |
| 816 | uint32_t use_vw_count; |
| 817 | uint32_t slave_config; |
| 818 | |
| 819 | if (!mb_cfg->vw_ch_en) |
| 820 | return 0; |
| 821 | |
| 822 | if (!espi_slave_supports_vw_channel(slave_caps)) { |
| 823 | printk(BIOS_ERR, "Error: eSPI slave doesn't support VW channel!\n"); |
| 824 | return -1; |
| 825 | } |
| 826 | |
| 827 | if (espi_get_configuration(ESPI_SLAVE_VW_CFG, &slave_vw_caps) == -1) |
| 828 | return -1; |
| 829 | |
| 830 | ctrlr_vw_caps = espi_read32(ESPI_MASTER_CAP); |
| 831 | ctrlr_vw_count_supp = (ctrlr_vw_caps & ESPI_VW_MAX_SIZE_MASK) >> ESPI_VW_MAX_SIZE_SHIFT; |
| 832 | |
| 833 | slave_vw_count_supp = espi_slave_get_vw_count_supp(slave_vw_caps); |
| 834 | use_vw_count = MIN(ctrlr_vw_count_supp, slave_vw_count_supp); |
| 835 | |
| 836 | slave_config = ESPI_SLAVE_CHANNEL_ENABLE | ESPI_SLAVE_VW_COUNT_SEL_VAL(use_vw_count); |
| 837 | return espi_set_channel_configuration(slave_config, ESPI_SLAVE_VW_CFG, ESPI_VW_CH_EN); |
| 838 | } |
| 839 | |
| 840 | static int espi_setup_periph_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) |
| 841 | { |
| 842 | uint32_t slave_config; |
| 843 | /* Peripheral channel requires BME bit to be set when enabling the channel. */ |
Raul E Rangel | 8fef0b7 | 2021-05-24 13:02:40 -0600 | [diff] [blame] | 844 | const uint32_t slave_en_mask = |
| 845 | ESPI_SLAVE_CHANNEL_ENABLE | ESPI_SLAVE_PERIPH_BUS_MASTER_ENABLE; |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 846 | |
| 847 | if (espi_get_configuration(ESPI_SLAVE_PERIPH_CFG, &slave_config) == -1) |
| 848 | return -1; |
| 849 | |
| 850 | /* |
| 851 | * Peripheral channel is the only one which is enabled on reset. So, if the mainboard |
| 852 | * wants to disable it, set configuration to disable peripheral channel. It also |
| 853 | * requires that BME bit be cleared. |
| 854 | */ |
| 855 | if (mb_cfg->periph_ch_en) { |
| 856 | if (!espi_slave_supports_periph_channel(slave_caps)) { |
| 857 | printk(BIOS_ERR, "Error: eSPI slave doesn't support periph channel!\n"); |
| 858 | return -1; |
| 859 | } |
| 860 | slave_config |= slave_en_mask; |
| 861 | } else { |
| 862 | slave_config &= ~slave_en_mask; |
| 863 | } |
| 864 | |
Raul E Rangel | 7222f7e | 2021-04-09 14:15:42 -0600 | [diff] [blame] | 865 | espi_show_slave_peripheral_channel_configuration(slave_config); |
| 866 | |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 867 | return espi_set_channel_configuration(slave_config, ESPI_SLAVE_PERIPH_CFG, |
| 868 | ESPI_PERIPH_CH_EN); |
| 869 | } |
| 870 | |
| 871 | static int espi_setup_oob_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) |
| 872 | { |
| 873 | uint32_t slave_config; |
| 874 | |
| 875 | if (!mb_cfg->oob_ch_en) |
| 876 | return 0; |
| 877 | |
| 878 | if (!espi_slave_supports_oob_channel(slave_caps)) { |
| 879 | printk(BIOS_ERR, "Error: eSPI slave doesn't support OOB channel!\n"); |
| 880 | return -1; |
| 881 | } |
| 882 | |
| 883 | if (espi_get_configuration(ESPI_SLAVE_OOB_CFG, &slave_config) == -1) |
| 884 | return -1; |
| 885 | |
| 886 | slave_config |= ESPI_SLAVE_CHANNEL_ENABLE; |
| 887 | |
| 888 | return espi_set_channel_configuration(slave_config, ESPI_SLAVE_OOB_CFG, |
| 889 | ESPI_OOB_CH_EN); |
| 890 | } |
| 891 | |
| 892 | static int espi_setup_flash_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) |
| 893 | { |
| 894 | uint32_t slave_config; |
| 895 | |
| 896 | if (!mb_cfg->flash_ch_en) |
| 897 | return 0; |
| 898 | |
| 899 | if (!espi_slave_supports_flash_channel(slave_caps)) { |
| 900 | printk(BIOS_ERR, "Error: eSPI slave doesn't support flash channel!\n"); |
| 901 | return -1; |
| 902 | } |
| 903 | |
| 904 | if (espi_get_configuration(ESPI_SLAVE_FLASH_CFG, &slave_config) == -1) |
| 905 | return -1; |
| 906 | |
| 907 | slave_config |= ESPI_SLAVE_CHANNEL_ENABLE; |
| 908 | |
| 909 | return espi_set_channel_configuration(slave_config, ESPI_SLAVE_FLASH_CFG, |
| 910 | ESPI_FLASH_CH_EN); |
| 911 | } |
| 912 | |
| 913 | static void espi_set_initial_config(const struct espi_config *mb_cfg) |
| 914 | { |
| 915 | uint32_t espi_initial_mode = ESPI_OP_FREQ_16_MHZ | ESPI_IO_MODE_SINGLE; |
| 916 | |
Raul E Rangel | dcec409 | 2021-05-07 15:35:10 -0600 | [diff] [blame] | 917 | switch (mb_cfg->alert_pin) { |
| 918 | case ESPI_ALERT_PIN_IN_BAND: |
| 919 | break; |
| 920 | case ESPI_ALERT_PIN_PUSH_PULL: |
| 921 | case ESPI_ALERT_PIN_OPEN_DRAIN: |
| 922 | espi_initial_mode |= ESPI_ALERT_MODE; |
| 923 | break; |
| 924 | default: |
| 925 | die("Unknown espi alert config: %u!\n", mb_cfg->alert_pin); |
| 926 | } |
| 927 | |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 928 | espi_write32(ESPI_SLAVE0_CONFIG, espi_initial_mode); |
| 929 | } |
| 930 | |
| 931 | static void espi_setup_subtractive_decode(const struct espi_config *mb_cfg) |
| 932 | { |
| 933 | uint32_t global_ctrl_reg; |
| 934 | global_ctrl_reg = espi_read32(ESPI_GLOBAL_CONTROL_1); |
| 935 | |
| 936 | if (mb_cfg->subtractive_decode) { |
| 937 | global_ctrl_reg &= ~ESPI_SUB_DECODE_SLV_MASK; |
| 938 | global_ctrl_reg |= ESPI_SUB_DECODE_EN; |
| 939 | |
| 940 | } else { |
| 941 | global_ctrl_reg &= ~ESPI_SUB_DECODE_EN; |
| 942 | } |
| 943 | espi_write32(ESPI_GLOBAL_CONTROL_1, global_ctrl_reg); |
| 944 | } |
| 945 | |
| 946 | int espi_setup(void) |
| 947 | { |
| 948 | uint32_t slave_caps; |
| 949 | const struct espi_config *cfg = espi_get_config(); |
| 950 | |
Martin Roth | 7a2bfeb | 2021-05-14 10:57:31 -0600 | [diff] [blame] | 951 | printk(BIOS_SPEW, "Initializing ESPI.\n"); |
| 952 | |
Raul E Rangel | b92383a | 2021-04-02 10:32:03 -0600 | [diff] [blame] | 953 | espi_write32(ESPI_GLOBAL_CONTROL_0, ESPI_AL_STOP_EN); |
| 954 | espi_write32(ESPI_GLOBAL_CONTROL_1, ESPI_RGCMD_INT(23) | ESPI_ERR_INT_SMI); |
| 955 | espi_write32(ESPI_SLAVE0_INT_EN, 0); |
| 956 | espi_clear_status(); |
Raul E Rangel | b95f848 | 2021-04-02 13:47:09 -0600 | [diff] [blame] | 957 | espi_clear_decodes(); |
Raul E Rangel | b92383a | 2021-04-02 10:32:03 -0600 | [diff] [blame] | 958 | |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 959 | /* |
| 960 | * Boot sequence: Step 1 |
| 961 | * Set correct initial configuration to talk to the slave: |
| 962 | * Set clock frequency to 16.7MHz and single IO mode. |
| 963 | */ |
| 964 | espi_set_initial_config(cfg); |
| 965 | |
| 966 | /* |
| 967 | * Boot sequence: Step 2 |
| 968 | * Send in-band reset |
| 969 | * The resets affects both host and slave devices, so set initial config again. |
| 970 | */ |
| 971 | if (espi_send_reset() == -1) { |
| 972 | printk(BIOS_ERR, "Error: In-band reset failed!\n"); |
| 973 | return -1; |
| 974 | } |
| 975 | espi_set_initial_config(cfg); |
| 976 | |
| 977 | /* |
| 978 | * Boot sequence: Step 3 |
| 979 | * Get configuration of slave device. |
| 980 | */ |
| 981 | if (espi_get_general_configuration(&slave_caps) == -1) { |
| 982 | printk(BIOS_ERR, "Error: Slave GET_CONFIGURATION failed!\n"); |
| 983 | return -1; |
| 984 | } |
| 985 | |
| 986 | /* |
| 987 | * Boot sequence: |
| 988 | * Step 4: Write slave device general config |
| 989 | * Step 5: Set host slave config |
| 990 | */ |
| 991 | if (espi_set_general_configuration(cfg, slave_caps) == -1) { |
| 992 | printk(BIOS_ERR, "Error: Slave SET_CONFIGURATION failed!\n"); |
| 993 | return -1; |
| 994 | } |
| 995 | |
| 996 | /* |
| 997 | * Setup polarity before enabling the VW channel so any interrupts |
| 998 | * received will have the correct polarity. |
| 999 | */ |
| 1000 | espi_write32(ESPI_RXVW_POLARITY, cfg->vw_irq_polarity); |
| 1001 | |
| 1002 | /* |
| 1003 | * Boot Sequences: Steps 6 - 9 |
| 1004 | * Channel setup |
| 1005 | */ |
| 1006 | /* Set up VW first so we can deassert PLTRST#. */ |
| 1007 | if (espi_setup_vw_channel(cfg, slave_caps) == -1) { |
| 1008 | printk(BIOS_ERR, "Error: Setup VW channel failed!\n"); |
| 1009 | return -1; |
| 1010 | } |
| 1011 | |
Raul E Rangel | 43aa527 | 2021-05-21 17:04:28 -0600 | [diff] [blame] | 1012 | /* Assert PLTRST# if VW channel is enabled by mainboard. */ |
| 1013 | if (espi_send_pltrst(cfg, true) == -1) { |
| 1014 | printk(BIOS_ERR, "Error: PLTRST# assertion failed!\n"); |
| 1015 | return -1; |
| 1016 | } |
| 1017 | |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 1018 | /* De-assert PLTRST# if VW channel is enabled by mainboard. */ |
Raul E Rangel | 43aa527 | 2021-05-21 17:04:28 -0600 | [diff] [blame] | 1019 | if (espi_send_pltrst(cfg, false) == -1) { |
| 1020 | printk(BIOS_ERR, "Error: PLTRST# deassertion failed!\n"); |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 1021 | return -1; |
| 1022 | } |
| 1023 | |
| 1024 | if (espi_setup_periph_channel(cfg, slave_caps) == -1) { |
| 1025 | printk(BIOS_ERR, "Error: Setup Periph channel failed!\n"); |
| 1026 | return -1; |
| 1027 | } |
| 1028 | |
| 1029 | if (espi_setup_oob_channel(cfg, slave_caps) == -1) { |
| 1030 | printk(BIOS_ERR, "Error: Setup OOB channel failed!\n"); |
| 1031 | return -1; |
| 1032 | } |
| 1033 | |
| 1034 | if (espi_setup_flash_channel(cfg, slave_caps) == -1) { |
| 1035 | printk(BIOS_ERR, "Error: Setup Flash channel failed!\n"); |
| 1036 | return -1; |
| 1037 | } |
| 1038 | |
Raul E Rangel | 61ac1bc | 2021-04-02 10:55:27 -0600 | [diff] [blame] | 1039 | if (espi_configure_decodes(cfg) == -1) { |
| 1040 | printk(BIOS_ERR, "Error: Configuring decodes failed!\n"); |
| 1041 | return -1; |
| 1042 | } |
| 1043 | |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 1044 | /* Enable subtractive decode if configured */ |
Felix Held | a2642d0 | 2021-02-17 00:32:46 +0100 | [diff] [blame] | 1045 | espi_setup_subtractive_decode(cfg); |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 1046 | |
Raul E Rangel | b92383a | 2021-04-02 10:32:03 -0600 | [diff] [blame] | 1047 | espi_write32(ESPI_GLOBAL_CONTROL_1, |
| 1048 | espi_read32(ESPI_GLOBAL_CONTROL_1) | ESPI_BUS_MASTER_EN); |
| 1049 | |
Martin Roth | 7a2bfeb | 2021-05-14 10:57:31 -0600 | [diff] [blame] | 1050 | printk(BIOS_SPEW, "Finished initializing ESPI.\n"); |
| 1051 | |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 1052 | return 0; |
| 1053 | } |
Felix Held | 1c03da5 | 2021-10-14 21:48:13 +0200 | [diff] [blame] | 1054 | |
| 1055 | /* Setup eSPI with any mainboard specific initialization. */ |
| 1056 | void configure_espi_with_mb_hook(void) |
| 1057 | { |
| 1058 | mb_set_up_early_espi(); |
| 1059 | espi_setup(); |
| 1060 | } |