Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 2 | |
| 3 | #include <amdblocks/chip.h> |
| 4 | #include <amdblocks/espi.h> |
| 5 | #include <amdblocks/lpc.h> |
| 6 | #include <arch/mmio.h> |
| 7 | #include <console/console.h> |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 8 | #include <espi.h> |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 9 | #include <soc/pci_devs.h> |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 10 | #include <timer.h> |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 11 | #include <types.h> |
| 12 | |
Furquan Shaikh | 98bc961 | 2020-05-09 19:31:55 -0700 | [diff] [blame] | 13 | static uintptr_t espi_bar; |
| 14 | |
| 15 | void espi_update_static_bar(uintptr_t bar) |
| 16 | { |
| 17 | espi_bar = bar; |
| 18 | } |
| 19 | |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 20 | static uintptr_t espi_get_bar(void) |
| 21 | { |
Martin Roth | b39e10d | 2020-07-14 11:08:55 -0600 | [diff] [blame] | 22 | if (ENV_X86 && !espi_bar) |
| 23 | espi_update_static_bar(lpc_get_spibase() + ESPI_OFFSET_FROM_BAR); |
Furquan Shaikh | 98bc961 | 2020-05-09 19:31:55 -0700 | [diff] [blame] | 24 | return espi_bar; |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 25 | } |
| 26 | |
Felix Held | 92dd678 | 2020-08-10 20:27:58 +0200 | [diff] [blame] | 27 | static uint32_t espi_read32(unsigned int reg) |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 28 | { |
| 29 | return read32((void *)(espi_get_bar() + reg)); |
| 30 | } |
| 31 | |
Felix Held | 92dd678 | 2020-08-10 20:27:58 +0200 | [diff] [blame] | 32 | static void espi_write32(unsigned int reg, uint32_t val) |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 33 | { |
| 34 | write32((void *)(espi_get_bar() + reg), val); |
| 35 | } |
| 36 | |
Felix Held | 92dd678 | 2020-08-10 20:27:58 +0200 | [diff] [blame] | 37 | static uint16_t espi_read16(unsigned int reg) |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 38 | { |
| 39 | return read16((void *)(espi_get_bar() + reg)); |
| 40 | } |
| 41 | |
Felix Held | 92dd678 | 2020-08-10 20:27:58 +0200 | [diff] [blame] | 42 | static void espi_write16(unsigned int reg, uint16_t val) |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 43 | { |
| 44 | write16((void *)(espi_get_bar() + reg), val); |
| 45 | } |
| 46 | |
Felix Held | 92dd678 | 2020-08-10 20:27:58 +0200 | [diff] [blame] | 47 | static uint8_t espi_read8(unsigned int reg) |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 48 | { |
| 49 | return read8((void *)(espi_get_bar() + reg)); |
| 50 | } |
| 51 | |
Felix Held | 92dd678 | 2020-08-10 20:27:58 +0200 | [diff] [blame] | 52 | static void espi_write8(unsigned int reg, uint8_t val) |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 53 | { |
| 54 | write8((void *)(espi_get_bar() + reg), val); |
| 55 | } |
| 56 | |
Felix Held | f08fbf8 | 2020-08-10 20:30:36 +0200 | [diff] [blame] | 57 | static void espi_enable_decode(uint32_t decode_en) |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 58 | { |
| 59 | uint32_t val; |
| 60 | |
| 61 | val = espi_read32(ESPI_DECODE); |
| 62 | val |= decode_en; |
| 63 | espi_write32(ESPI_DECODE, val); |
| 64 | } |
| 65 | |
Felix Held | f08fbf8 | 2020-08-10 20:30:36 +0200 | [diff] [blame] | 66 | static bool espi_is_decode_enabled(uint32_t decode) |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 67 | { |
| 68 | uint32_t val; |
| 69 | |
| 70 | val = espi_read32(ESPI_DECODE); |
| 71 | return !!(val & decode); |
| 72 | } |
| 73 | |
| 74 | static int espi_find_io_window(uint16_t win_base) |
| 75 | { |
| 76 | int i; |
| 77 | |
| 78 | for (i = 0; i < ESPI_GENERIC_IO_WIN_COUNT; i++) { |
| 79 | if (!espi_is_decode_enabled(ESPI_DECODE_IO_RANGE_EN(i))) |
| 80 | continue; |
| 81 | |
| 82 | if (espi_read16(ESPI_IO_RANGE_BASE(i)) == win_base) |
| 83 | return i; |
| 84 | } |
| 85 | |
| 86 | return -1; |
| 87 | } |
| 88 | |
| 89 | static int espi_get_unused_io_window(void) |
| 90 | { |
| 91 | int i; |
| 92 | |
| 93 | for (i = 0; i < ESPI_GENERIC_IO_WIN_COUNT; i++) { |
| 94 | if (!espi_is_decode_enabled(ESPI_DECODE_IO_RANGE_EN(i))) |
| 95 | return i; |
| 96 | } |
| 97 | |
| 98 | return -1; |
| 99 | } |
| 100 | |
Raul E Rangel | b95f848 | 2021-04-02 13:47:09 -0600 | [diff] [blame] | 101 | static void espi_clear_decodes(void) |
Martin Roth | 011bf13 | 2021-03-23 13:20:42 -0600 | [diff] [blame] | 102 | { |
| 103 | unsigned int idx; |
| 104 | |
| 105 | /* First turn off all enable bits, then zero base, range, and size registers */ |
Raul E Rangel | 01792e3 | 2021-04-26 13:52:38 -0600 | [diff] [blame] | 106 | espi_write16(ESPI_DECODE, 0); |
Martin Roth | 011bf13 | 2021-03-23 13:20:42 -0600 | [diff] [blame] | 107 | |
| 108 | for (idx = 0; idx < ESPI_GENERIC_IO_WIN_COUNT; idx++) { |
| 109 | espi_write16(ESPI_IO_RANGE_BASE(idx), 0); |
| 110 | espi_write8(ESPI_IO_RANGE_SIZE(idx), 0); |
| 111 | } |
| 112 | for (idx = 0; idx < ESPI_GENERIC_MMIO_WIN_COUNT; idx++) { |
| 113 | espi_write32(ESPI_MMIO_RANGE_BASE(idx), 0); |
| 114 | espi_write16(ESPI_MMIO_RANGE_SIZE(idx), 0); |
| 115 | } |
| 116 | } |
| 117 | |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 118 | /* |
| 119 | * Returns decode enable bits for standard IO port addresses. If port address is not supported |
| 120 | * by standard decode or if the size of window is not 1, then it returns -1. |
| 121 | */ |
| 122 | static int espi_std_io_decode(uint16_t base, size_t size) |
| 123 | { |
Felix Held | c0d4eeb | 2020-08-10 20:37:16 +0200 | [diff] [blame] | 124 | if (size == 2 && base == 0x2e) |
| 125 | return ESPI_DECODE_IO_0X2E_0X2F_EN; |
| 126 | |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 127 | if (size != 1) |
Felix Held | 4bf419f | 2020-08-10 20:33:25 +0200 | [diff] [blame] | 128 | return -1; |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 129 | |
| 130 | switch (base) { |
| 131 | case 0x80: |
Felix Held | 4bf419f | 2020-08-10 20:33:25 +0200 | [diff] [blame] | 132 | return ESPI_DECODE_IO_0x80_EN; |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 133 | case 0x60: |
| 134 | case 0x64: |
Felix Held | 4bf419f | 2020-08-10 20:33:25 +0200 | [diff] [blame] | 135 | return ESPI_DECODE_IO_0X60_0X64_EN; |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 136 | case 0x2e: |
| 137 | case 0x2f: |
Felix Held | 4bf419f | 2020-08-10 20:33:25 +0200 | [diff] [blame] | 138 | return ESPI_DECODE_IO_0X2E_0X2F_EN; |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 139 | default: |
Felix Held | 4bf419f | 2020-08-10 20:33:25 +0200 | [diff] [blame] | 140 | return -1; |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 141 | } |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 142 | } |
| 143 | |
| 144 | static size_t espi_get_io_window_size(int idx) |
| 145 | { |
| 146 | return espi_read8(ESPI_IO_RANGE_SIZE(idx)) + 1; |
| 147 | } |
| 148 | |
| 149 | static void espi_write_io_window(int idx, uint16_t base, size_t size) |
| 150 | { |
| 151 | espi_write16(ESPI_IO_RANGE_BASE(idx), base); |
| 152 | espi_write8(ESPI_IO_RANGE_SIZE(idx), size - 1); |
| 153 | } |
| 154 | |
| 155 | static int espi_open_generic_io_window(uint16_t base, size_t size) |
| 156 | { |
| 157 | size_t win_size; |
| 158 | int idx; |
| 159 | |
| 160 | for (; size; size -= win_size, base += win_size) { |
| 161 | win_size = MIN(size, ESPI_GENERIC_IO_MAX_WIN_SIZE); |
| 162 | |
| 163 | idx = espi_find_io_window(base); |
| 164 | if (idx != -1) { |
| 165 | size_t curr_size = espi_get_io_window_size(idx); |
| 166 | |
| 167 | if (curr_size > win_size) { |
| 168 | printk(BIOS_INFO, "eSPI window already configured to be larger than requested! "); |
| 169 | printk(BIOS_INFO, "Base: 0x%x, Requested size: 0x%zx, Actual size: 0x%zx\n", |
| 170 | base, win_size, curr_size); |
| 171 | } else if (curr_size < win_size) { |
| 172 | espi_write_io_window(idx, base, win_size); |
| 173 | printk(BIOS_INFO, "eSPI window at base: 0x%x resized from 0x%zx to 0x%zx\n", |
| 174 | base, curr_size, win_size); |
| 175 | } |
| 176 | |
| 177 | continue; |
| 178 | } |
| 179 | |
| 180 | idx = espi_get_unused_io_window(); |
| 181 | if (idx == -1) { |
| 182 | printk(BIOS_ERR, "Cannot open IO window base %x size %zx\n", base, |
| 183 | size); |
| 184 | printk(BIOS_ERR, "ERROR: No more available IO windows!\n"); |
| 185 | return -1; |
| 186 | } |
| 187 | |
| 188 | espi_write_io_window(idx, base, win_size); |
| 189 | espi_enable_decode(ESPI_DECODE_IO_RANGE_EN(idx)); |
| 190 | } |
| 191 | |
| 192 | return 0; |
| 193 | } |
| 194 | |
| 195 | int espi_open_io_window(uint16_t base, size_t size) |
| 196 | { |
| 197 | int std_io; |
| 198 | |
| 199 | std_io = espi_std_io_decode(base, size); |
| 200 | if (std_io != -1) { |
| 201 | espi_enable_decode(std_io); |
| 202 | return 0; |
Felix Held | b026c7c | 2020-08-10 20:43:53 +0200 | [diff] [blame] | 203 | } else { |
| 204 | return espi_open_generic_io_window(base, size); |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 205 | } |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 206 | } |
| 207 | |
| 208 | static int espi_find_mmio_window(uint32_t win_base) |
| 209 | { |
| 210 | int i; |
| 211 | |
| 212 | for (i = 0; i < ESPI_GENERIC_MMIO_WIN_COUNT; i++) { |
| 213 | if (!espi_is_decode_enabled(ESPI_DECODE_MMIO_RANGE_EN(i))) |
| 214 | continue; |
| 215 | |
| 216 | if (espi_read32(ESPI_MMIO_RANGE_BASE(i)) == win_base) |
| 217 | return i; |
| 218 | } |
| 219 | |
| 220 | return -1; |
| 221 | } |
| 222 | |
| 223 | static int espi_get_unused_mmio_window(void) |
| 224 | { |
| 225 | int i; |
| 226 | |
| 227 | for (i = 0; i < ESPI_GENERIC_MMIO_WIN_COUNT; i++) { |
| 228 | if (!espi_is_decode_enabled(ESPI_DECODE_MMIO_RANGE_EN(i))) |
| 229 | return i; |
| 230 | } |
| 231 | |
| 232 | return -1; |
| 233 | |
| 234 | } |
| 235 | |
| 236 | static size_t espi_get_mmio_window_size(int idx) |
| 237 | { |
| 238 | return espi_read16(ESPI_MMIO_RANGE_SIZE(idx)) + 1; |
| 239 | } |
| 240 | |
| 241 | static void espi_write_mmio_window(int idx, uint32_t base, size_t size) |
| 242 | { |
| 243 | espi_write32(ESPI_MMIO_RANGE_BASE(idx), base); |
| 244 | espi_write16(ESPI_MMIO_RANGE_SIZE(idx), size - 1); |
| 245 | } |
| 246 | |
| 247 | int espi_open_mmio_window(uint32_t base, size_t size) |
| 248 | { |
| 249 | size_t win_size; |
| 250 | int idx; |
| 251 | |
| 252 | for (; size; size -= win_size, base += win_size) { |
| 253 | win_size = MIN(size, ESPI_GENERIC_MMIO_MAX_WIN_SIZE); |
| 254 | |
| 255 | idx = espi_find_mmio_window(base); |
| 256 | if (idx != -1) { |
| 257 | size_t curr_size = espi_get_mmio_window_size(idx); |
| 258 | |
| 259 | if (curr_size > win_size) { |
| 260 | printk(BIOS_INFO, "eSPI window already configured to be larger than requested! "); |
| 261 | printk(BIOS_INFO, "Base: 0x%x, Requested size: 0x%zx, Actual size: 0x%zx\n", |
| 262 | base, win_size, curr_size); |
| 263 | } else if (curr_size < win_size) { |
| 264 | espi_write_mmio_window(idx, base, win_size); |
| 265 | printk(BIOS_INFO, "eSPI window at base: 0x%x resized from 0x%zx to 0x%zx\n", |
| 266 | base, curr_size, win_size); |
| 267 | } |
| 268 | |
| 269 | continue; |
| 270 | } |
| 271 | |
| 272 | idx = espi_get_unused_mmio_window(); |
| 273 | if (idx == -1) { |
| 274 | printk(BIOS_ERR, "Cannot open IO window base %x size %zx\n", base, |
| 275 | size); |
| 276 | printk(BIOS_ERR, "ERROR: No more available MMIO windows!\n"); |
| 277 | return -1; |
| 278 | } |
| 279 | |
| 280 | espi_write_mmio_window(idx, base, win_size); |
| 281 | espi_enable_decode(ESPI_DECODE_MMIO_RANGE_EN(idx)); |
| 282 | } |
| 283 | |
| 284 | return 0; |
| 285 | } |
| 286 | |
| 287 | static const struct espi_config *espi_get_config(void) |
| 288 | { |
| 289 | const struct soc_amd_common_config *soc_cfg = soc_get_common_config(); |
| 290 | |
| 291 | if (!soc_cfg) |
| 292 | die("Common config structure is NULL!\n"); |
| 293 | |
| 294 | return &soc_cfg->espi_config; |
| 295 | } |
| 296 | |
Raul E Rangel | 61ac1bc | 2021-04-02 10:55:27 -0600 | [diff] [blame] | 297 | static int espi_configure_decodes(const struct espi_config *cfg) |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 298 | { |
Raul E Rangel | 61ac1bc | 2021-04-02 10:55:27 -0600 | [diff] [blame] | 299 | int i, ret; |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 300 | |
| 301 | espi_enable_decode(cfg->std_io_decode_bitmap); |
| 302 | |
| 303 | for (i = 0; i < ESPI_GENERIC_IO_WIN_COUNT; i++) { |
| 304 | if (cfg->generic_io_range[i].size == 0) |
| 305 | continue; |
Raul E Rangel | 61ac1bc | 2021-04-02 10:55:27 -0600 | [diff] [blame] | 306 | ret = espi_open_generic_io_window(cfg->generic_io_range[i].base, |
| 307 | cfg->generic_io_range[i].size); |
| 308 | if (ret) |
| 309 | return ret; |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 310 | } |
Raul E Rangel | 61ac1bc | 2021-04-02 10:55:27 -0600 | [diff] [blame] | 311 | |
| 312 | return 0; |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 313 | } |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 314 | |
| 315 | #define ESPI_DN_TX_HDR0 0x00 |
| 316 | enum espi_cmd_type { |
| 317 | CMD_TYPE_SET_CONFIGURATION = 0, |
| 318 | CMD_TYPE_GET_CONFIGURATION = 1, |
| 319 | CMD_TYPE_IN_BAND_RESET = 2, |
| 320 | CMD_TYPE_PERIPHERAL = 4, |
| 321 | CMD_TYPE_VW = 5, |
| 322 | CMD_TYPE_OOB = 6, |
| 323 | CMD_TYPE_FLASH = 7, |
| 324 | }; |
| 325 | |
| 326 | #define ESPI_DN_TX_HDR1 0x04 |
| 327 | #define ESPI_DN_TX_HDR2 0x08 |
| 328 | #define ESPI_DN_TX_DATA 0x0c |
| 329 | |
| 330 | #define ESPI_MASTER_CAP 0x2c |
| 331 | #define ESPI_VW_MAX_SIZE_SHIFT 13 |
| 332 | #define ESPI_VW_MAX_SIZE_MASK (0x3f << ESPI_VW_MAX_SIZE_SHIFT) |
| 333 | |
Raul E Rangel | 1d0e493 | 2021-04-02 10:27:11 -0600 | [diff] [blame] | 334 | #define ESPI_GLOBAL_CONTROL_0 0x30 |
| 335 | #define ESPI_WAIT_CNT_SHIFT 24 |
| 336 | #define ESPI_WAIT_CNT_MASK (0x3F << ESPI_WAIT_CNT_SHIFT) |
| 337 | #define ESPI_WDG_CNT_SHIFT 8 |
| 338 | #define ESPI_WDG_CNT_MASK (0xFFFF << ESPI_WDG_CNT_SHIFT) |
| 339 | #define ESPI_AL_IDLE_TIMER_SHIFT 4 |
| 340 | #define ESPI_AL_IDLE_TIMER_MASK (0x7 << ESPI_AL_IDLE_TIMER_SHIFT) |
| 341 | #define ESPI_AL_STOP_EN (1 << 3) |
| 342 | #define ESPI_PR_CLKGAT_EN (1 << 2) |
| 343 | #define ESPI_WAIT_CHKEN (1 << 1) |
| 344 | #define ESPI_WDG_EN (1 << 0) |
| 345 | |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 346 | #define ESPI_GLOBAL_CONTROL_1 0x34 |
Raul E Rangel | 1d0e493 | 2021-04-02 10:27:11 -0600 | [diff] [blame] | 347 | #define ESPI_RGCMD_INT_MAP_SHIFT 13 |
| 348 | #define ESPI_RGCMD_INT_MAP_MASK (0x1F << ESPI_RGCMD_INT_MAP_SHIFT) |
| 349 | #define ESPI_RGCMD_INT(irq) ((irq) << ESPI_RGCMD_INT_MAP_SHIFT) |
| 350 | #define ESPI_RGCMD_INT_SMI (0x1F << ESPI_RGCMD_INT_MAP_SHIFT) |
| 351 | #define ESPI_ERR_INT_MAP_SHIFT 8 |
| 352 | #define ESPI_ERR_INT_MAP_MASK (0x1F << ESPI_ERR_INT_MAP_SHIFT) |
| 353 | #define ESPI_ERR_INT(irq) ((irq) << ESPI_ERR_INT_MAP_SHIFT) |
| 354 | #define ESPI_ERR_INT_SMI (0x1F << ESPI_ERR_INT_MAP_SHIFT) |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 355 | #define ESPI_SUB_DECODE_SLV_SHIFT 3 |
| 356 | #define ESPI_SUB_DECODE_SLV_MASK (0x3 << ESPI_SUB_DECODE_SLV_SHIFT) |
| 357 | #define ESPI_SUB_DECODE_EN (1 << 2) |
Raul E Rangel | 1d0e493 | 2021-04-02 10:27:11 -0600 | [diff] [blame] | 358 | #define ESPI_BUS_MASTER_EN (1 << 1) |
| 359 | #define ESPI_SW_RST (1 << 0) |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 360 | |
Raul E Rangel | 1d0e493 | 2021-04-02 10:27:11 -0600 | [diff] [blame] | 361 | #define ESPI_SLAVE0_INT_EN 0x6C |
Raul E Rangel | 4774012 | 2021-04-02 10:16:54 -0600 | [diff] [blame] | 362 | #define ESPI_SLAVE0_INT_STS 0x70 |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 363 | #define ESPI_STATUS_DNCMD_COMPLETE (1 << 28) |
| 364 | #define ESPI_STATUS_NON_FATAL_ERROR (1 << 6) |
| 365 | #define ESPI_STATUS_FATAL_ERROR (1 << 5) |
| 366 | #define ESPI_STATUS_NO_RESPONSE (1 << 4) |
| 367 | #define ESPI_STATUS_CRC_ERR (1 << 2) |
| 368 | #define ESPI_STATUS_WAIT_TIMEOUT (1 << 1) |
| 369 | #define ESPI_STATUS_BUS_ERROR (1 << 0) |
| 370 | |
| 371 | #define ESPI_RXVW_POLARITY 0xac |
| 372 | |
| 373 | #define ESPI_CMD_TIMEOUT_US 100 |
Raul E Rangel | 0318dc1 | 2021-05-21 16:31:52 -0600 | [diff] [blame^] | 374 | #define ESPI_CH_READY_TIMEOUT_US 10000 |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 375 | |
| 376 | union espi_txhdr0 { |
| 377 | uint32_t val; |
| 378 | struct { |
| 379 | uint32_t cmd_type:3; |
| 380 | uint32_t cmd_sts:1; |
| 381 | uint32_t slave_sel:2; |
| 382 | uint32_t rsvd:2; |
| 383 | uint32_t hdata0:8; |
| 384 | uint32_t hdata1:8; |
| 385 | uint32_t hdata2:8; |
| 386 | }; |
| 387 | } __packed; |
| 388 | |
| 389 | union espi_txhdr1 { |
| 390 | uint32_t val; |
| 391 | struct { |
| 392 | uint32_t hdata3:8; |
| 393 | uint32_t hdata4:8; |
| 394 | uint32_t hdata5:8; |
| 395 | uint32_t hdata6:8; |
| 396 | }; |
| 397 | } __packed; |
| 398 | |
| 399 | union espi_txhdr2 { |
| 400 | uint32_t val; |
| 401 | struct { |
| 402 | uint32_t hdata7:8; |
| 403 | uint32_t rsvd:24; |
| 404 | }; |
| 405 | } __packed; |
| 406 | |
| 407 | union espi_txdata { |
| 408 | uint32_t val; |
| 409 | struct { |
| 410 | uint32_t byte0:8; |
| 411 | uint32_t byte1:8; |
| 412 | uint32_t byte2:8; |
| 413 | uint32_t byte3:8; |
| 414 | }; |
| 415 | } __packed; |
| 416 | |
| 417 | struct espi_cmd { |
| 418 | union espi_txhdr0 hdr0; |
| 419 | union espi_txhdr1 hdr1; |
| 420 | union espi_txhdr2 hdr2; |
| 421 | union espi_txdata data; |
Raul E Rangel | 12c0542 | 2021-05-11 11:13:38 -0600 | [diff] [blame] | 422 | uint32_t expected_status_codes; |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 423 | } __packed; |
| 424 | |
| 425 | /* Wait up to ESPI_CMD_TIMEOUT_US for hardware to clear DNCMD_STATUS bit. */ |
| 426 | static int espi_wait_ready(void) |
| 427 | { |
| 428 | struct stopwatch sw; |
| 429 | union espi_txhdr0 hdr0; |
| 430 | |
| 431 | stopwatch_init_usecs_expire(&sw, ESPI_CMD_TIMEOUT_US); |
| 432 | do { |
| 433 | hdr0.val = espi_read32(ESPI_DN_TX_HDR0); |
| 434 | if (!hdr0.cmd_sts) |
| 435 | return 0; |
| 436 | } while (!stopwatch_expired(&sw)); |
| 437 | |
| 438 | return -1; |
| 439 | } |
| 440 | |
| 441 | /* Clear interrupt status register */ |
| 442 | static void espi_clear_status(void) |
| 443 | { |
Raul E Rangel | 4774012 | 2021-04-02 10:16:54 -0600 | [diff] [blame] | 444 | uint32_t status = espi_read32(ESPI_SLAVE0_INT_STS); |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 445 | if (status) |
Raul E Rangel | 4774012 | 2021-04-02 10:16:54 -0600 | [diff] [blame] | 446 | espi_write32(ESPI_SLAVE0_INT_STS, status); |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 447 | } |
| 448 | |
| 449 | /* |
| 450 | * Wait up to ESPI_CMD_TIMEOUT_US for interrupt status register to update after sending a |
| 451 | * command. |
| 452 | */ |
Felix Held | 1ba3833 | 2020-08-10 20:45:30 +0200 | [diff] [blame] | 453 | static int espi_poll_status(uint32_t *status) |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 454 | { |
| 455 | struct stopwatch sw; |
| 456 | |
| 457 | stopwatch_init_usecs_expire(&sw, ESPI_CMD_TIMEOUT_US); |
| 458 | do { |
Raul E Rangel | 4774012 | 2021-04-02 10:16:54 -0600 | [diff] [blame] | 459 | *status = espi_read32(ESPI_SLAVE0_INT_STS); |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 460 | if (*status) |
| 461 | return 0; |
| 462 | } while (!stopwatch_expired(&sw)); |
| 463 | |
| 464 | printk(BIOS_ERR, "Error: eSPI timed out waiting for status update.\n"); |
| 465 | |
| 466 | return -1; |
| 467 | } |
| 468 | |
| 469 | static void espi_show_failure(const struct espi_cmd *cmd, const char *str, uint32_t status) |
| 470 | { |
| 471 | printk(BIOS_ERR, "eSPI cmd0-cmd2: %08x %08x %08x data: %08x.\n", |
| 472 | cmd->hdr0.val, cmd->hdr1.val, cmd->hdr2.val, cmd->data.val); |
| 473 | printk(BIOS_ERR, "%s (Status = 0x%x)\n", str, status); |
| 474 | } |
| 475 | |
| 476 | static int espi_send_command(const struct espi_cmd *cmd) |
| 477 | { |
| 478 | uint32_t status; |
| 479 | |
| 480 | if (CONFIG(ESPI_DEBUG)) |
| 481 | printk(BIOS_ERR, "eSPI cmd0-cmd2: %08x %08x %08x data: %08x.\n", |
| 482 | cmd->hdr0.val, cmd->hdr1.val, cmd->hdr2.val, cmd->data.val); |
| 483 | |
| 484 | if (espi_wait_ready() == -1) { |
| 485 | espi_show_failure(cmd, "Error: eSPI was not ready to accept a command", 0); |
| 486 | return -1; |
| 487 | } |
| 488 | |
| 489 | espi_clear_status(); |
| 490 | |
| 491 | espi_write32(ESPI_DN_TX_HDR1, cmd->hdr1.val); |
| 492 | espi_write32(ESPI_DN_TX_HDR2, cmd->hdr2.val); |
| 493 | espi_write32(ESPI_DN_TX_DATA, cmd->data.val); |
| 494 | |
| 495 | /* Dword 0 must be last as this write triggers the transaction */ |
| 496 | espi_write32(ESPI_DN_TX_HDR0, cmd->hdr0.val); |
| 497 | |
| 498 | if (espi_wait_ready() == -1) { |
| 499 | espi_show_failure(cmd, |
| 500 | "Error: eSPI timed out waiting for command to complete", 0); |
| 501 | return -1; |
| 502 | } |
| 503 | |
Felix Held | 1ba3833 | 2020-08-10 20:45:30 +0200 | [diff] [blame] | 504 | if (espi_poll_status(&status) == -1) { |
| 505 | espi_show_failure(cmd, "Error: eSPI poll status failed", 0); |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 506 | return -1; |
| 507 | } |
| 508 | |
| 509 | /* If command did not complete downstream, return error. */ |
| 510 | if (!(status & ESPI_STATUS_DNCMD_COMPLETE)) { |
| 511 | espi_show_failure(cmd, "Error: eSPI downstream command completion failure", |
| 512 | status); |
| 513 | return -1; |
| 514 | } |
| 515 | |
Raul E Rangel | 12c0542 | 2021-05-11 11:13:38 -0600 | [diff] [blame] | 516 | if (status & ~(ESPI_STATUS_DNCMD_COMPLETE | cmd->expected_status_codes)) { |
Felix Held | 316d59c | 2020-08-10 20:42:20 +0200 | [diff] [blame] | 517 | espi_show_failure(cmd, "Error: unexpected eSPI status register bits set", |
| 518 | status); |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 519 | return -1; |
| 520 | } |
| 521 | |
Raul E Rangel | 12c0542 | 2021-05-11 11:13:38 -0600 | [diff] [blame] | 522 | espi_write32(ESPI_SLAVE0_INT_STS, status); |
Raul E Rangel | 66c52ff | 2021-04-02 10:18:25 -0600 | [diff] [blame] | 523 | |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 524 | return 0; |
| 525 | } |
| 526 | |
| 527 | static int espi_send_reset(void) |
| 528 | { |
| 529 | struct espi_cmd cmd = { |
| 530 | .hdr0 = { |
| 531 | .cmd_type = CMD_TYPE_IN_BAND_RESET, |
| 532 | .cmd_sts = 1, |
| 533 | }, |
Raul E Rangel | 12c0542 | 2021-05-11 11:13:38 -0600 | [diff] [blame] | 534 | |
| 535 | /* |
| 536 | * When performing an in-band reset the host controller and the |
| 537 | * peripheral can have mismatched IO configs. |
| 538 | * |
| 539 | * i.e., The eSPI peripheral can be in IO-4 mode while, the |
| 540 | * eSPI host will be in IO-1. This results in the peripheral |
| 541 | * getting invalid packets and thus not responding. |
| 542 | * |
| 543 | * If the peripheral is alerting when we perform an in-band |
| 544 | * reset, there is a race condition in espi_send_command. |
| 545 | * 1) espi_send_command clears the interrupt status. |
| 546 | * 2) eSPI host controller hardware notices the alert and sends |
| 547 | * a GET_STATUS. |
| 548 | * 3) espi_send_command writes the in-band reset command. |
| 549 | * 4) eSPI hardware enqueues the in-band reset until GET_STATUS |
| 550 | * is complete. |
| 551 | * 5) GET_STATUS fails with NO_RESPONSE and sets the interrupt |
| 552 | * status. |
| 553 | * 6) eSPI hardware performs in-band reset. |
| 554 | * 7) espi_send_command checks the status and sees a |
| 555 | * NO_RESPONSE bit. |
| 556 | * |
| 557 | * As a workaround we allow the NO_RESPONSE status code when |
| 558 | * we perform an in-band reset. |
| 559 | */ |
| 560 | .expected_status_codes = ESPI_STATUS_NO_RESPONSE, |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 561 | }; |
| 562 | |
| 563 | return espi_send_command(&cmd); |
| 564 | } |
| 565 | |
| 566 | static int espi_send_pltrst_deassert(const struct espi_config *mb_cfg) |
| 567 | { |
| 568 | struct espi_cmd cmd = { |
| 569 | .hdr0 = { |
| 570 | .cmd_type = CMD_TYPE_VW, |
| 571 | .cmd_sts = 1, |
| 572 | .hdata0 = 0, /* 1 VW group */ |
| 573 | }, |
| 574 | .data = { |
| 575 | .byte0 = ESPI_VW_INDEX_SYSTEM_EVENT_3, |
| 576 | .byte1 = ESPI_VW_SIGNAL_HIGH(ESPI_VW_PLTRST), |
| 577 | }, |
| 578 | }; |
| 579 | |
| 580 | if (!mb_cfg->vw_ch_en) |
| 581 | return 0; |
| 582 | |
| 583 | return espi_send_command(&cmd); |
| 584 | } |
| 585 | |
| 586 | /* |
| 587 | * In case of get configuration command, hdata0 contains bits 15:8 of the slave register address |
| 588 | * and hdata1 contains bits 7:0 of the slave register address. |
| 589 | */ |
| 590 | #define ESPI_CONFIGURATION_HDATA0(a) (((a) >> 8) & 0xff) |
| 591 | #define ESPI_CONFIGURATION_HDATA1(a) ((a) & 0xff) |
| 592 | |
| 593 | static int espi_get_configuration(uint16_t slave_reg_addr, uint32_t *config) |
| 594 | { |
| 595 | struct espi_cmd cmd = { |
| 596 | .hdr0 = { |
| 597 | .cmd_type = CMD_TYPE_GET_CONFIGURATION, |
| 598 | .cmd_sts = 1, |
| 599 | .hdata0 = ESPI_CONFIGURATION_HDATA0(slave_reg_addr), |
| 600 | .hdata1 = ESPI_CONFIGURATION_HDATA1(slave_reg_addr), |
| 601 | }, |
| 602 | }; |
| 603 | |
| 604 | *config = 0; |
| 605 | |
| 606 | if (espi_send_command(&cmd)) |
| 607 | return -1; |
| 608 | |
| 609 | *config = espi_read32(ESPI_DN_TX_HDR1); |
| 610 | |
| 611 | if (CONFIG(ESPI_DEBUG)) |
| 612 | printk(BIOS_DEBUG, "Get configuration for slave register(0x%x): 0x%x\n", |
| 613 | slave_reg_addr, *config); |
| 614 | |
| 615 | return 0; |
| 616 | } |
| 617 | |
| 618 | static int espi_set_configuration(uint16_t slave_reg_addr, uint32_t config) |
| 619 | { |
| 620 | struct espi_cmd cmd = { |
| 621 | .hdr0 = { |
| 622 | .cmd_type = CMD_TYPE_SET_CONFIGURATION, |
| 623 | .cmd_sts = 1, |
| 624 | .hdata0 = ESPI_CONFIGURATION_HDATA0(slave_reg_addr), |
| 625 | .hdata1 = ESPI_CONFIGURATION_HDATA1(slave_reg_addr), |
| 626 | }, |
| 627 | .hdr1 = { |
| 628 | .val = config, |
| 629 | }, |
| 630 | }; |
| 631 | |
| 632 | return espi_send_command(&cmd); |
| 633 | } |
| 634 | |
| 635 | static int espi_get_general_configuration(uint32_t *config) |
| 636 | { |
| 637 | int ret = espi_get_configuration(ESPI_SLAVE_GENERAL_CFG, config); |
| 638 | if (ret == -1) |
| 639 | return -1; |
| 640 | |
| 641 | espi_show_slave_general_configuration(*config); |
| 642 | return 0; |
| 643 | } |
| 644 | |
| 645 | static void espi_set_io_mode_config(enum espi_io_mode mb_io_mode, uint32_t slave_caps, |
| 646 | uint32_t *slave_config, uint32_t *ctrlr_config) |
| 647 | { |
| 648 | switch (mb_io_mode) { |
| 649 | case ESPI_IO_MODE_QUAD: |
| 650 | if (espi_slave_supports_quad_io(slave_caps)) { |
| 651 | *slave_config |= ESPI_SLAVE_IO_MODE_SEL_QUAD; |
| 652 | *ctrlr_config |= ESPI_IO_MODE_QUAD; |
| 653 | break; |
| 654 | } |
| 655 | printk(BIOS_ERR, "Error: eSPI Quad I/O not supported. Dropping to dual mode.\n"); |
| 656 | /* Intentional fall-through */ |
| 657 | case ESPI_IO_MODE_DUAL: |
| 658 | if (espi_slave_supports_dual_io(slave_caps)) { |
| 659 | *slave_config |= ESPI_SLAVE_IO_MODE_SEL_DUAL; |
| 660 | *ctrlr_config |= ESPI_IO_MODE_DUAL; |
| 661 | break; |
| 662 | } |
| 663 | printk(BIOS_ERR, |
| 664 | "Error: eSPI Dual I/O not supported. Dropping to single mode.\n"); |
| 665 | /* Intentional fall-through */ |
| 666 | case ESPI_IO_MODE_SINGLE: |
| 667 | /* Single I/O mode is always supported. */ |
| 668 | *slave_config |= ESPI_SLAVE_IO_MODE_SEL_SINGLE; |
| 669 | *ctrlr_config |= ESPI_IO_MODE_SINGLE; |
| 670 | break; |
| 671 | default: |
| 672 | die("No supported eSPI I/O modes!\n"); |
| 673 | } |
| 674 | } |
| 675 | |
| 676 | static void espi_set_op_freq_config(enum espi_op_freq mb_op_freq, uint32_t slave_caps, |
| 677 | uint32_t *slave_config, uint32_t *ctrlr_config) |
| 678 | { |
| 679 | int slave_max_speed_mhz = espi_slave_max_speed_mhz_supported(slave_caps); |
| 680 | |
| 681 | switch (mb_op_freq) { |
| 682 | case ESPI_OP_FREQ_66_MHZ: |
| 683 | if (slave_max_speed_mhz >= 66) { |
| 684 | *slave_config |= ESPI_SLAVE_OP_FREQ_SEL_66_MHZ; |
| 685 | *ctrlr_config |= ESPI_OP_FREQ_66_MHZ; |
| 686 | break; |
| 687 | } |
| 688 | printk(BIOS_ERR, "Error: eSPI 66MHz not supported. Dropping to 33MHz.\n"); |
| 689 | /* Intentional fall-through */ |
| 690 | case ESPI_OP_FREQ_33_MHZ: |
| 691 | if (slave_max_speed_mhz >= 33) { |
| 692 | *slave_config |= ESPI_SLAVE_OP_FREQ_SEL_33_MHZ; |
| 693 | *ctrlr_config |= ESPI_OP_FREQ_33_MHZ; |
| 694 | break; |
| 695 | } |
| 696 | printk(BIOS_ERR, "Error: eSPI 33MHz not supported. Dropping to 16MHz.\n"); |
| 697 | /* Intentional fall-through */ |
| 698 | case ESPI_OP_FREQ_16_MHZ: |
| 699 | /* |
| 700 | * eSPI spec says the minimum frequency is 20MHz, but AMD datasheets support |
| 701 | * 16.7 Mhz. |
| 702 | */ |
| 703 | if (slave_max_speed_mhz > 0) { |
| 704 | *slave_config |= ESPI_SLAVE_OP_FREQ_SEL_20_MHZ; |
| 705 | *ctrlr_config |= ESPI_OP_FREQ_16_MHZ; |
| 706 | break; |
| 707 | } |
| 708 | /* Intentional fall-through */ |
| 709 | default: |
| 710 | die("No supported eSPI Operating Frequency!\n"); |
| 711 | } |
| 712 | } |
| 713 | |
Raul E Rangel | 8317e72 | 2021-05-05 13:38:27 -0600 | [diff] [blame] | 714 | static void espi_set_alert_pin_config(enum espi_alert_pin alert_pin, uint32_t slave_caps, |
| 715 | uint32_t *slave_config, uint32_t *ctrlr_config) |
| 716 | { |
| 717 | switch (alert_pin) { |
| 718 | case ESPI_ALERT_PIN_IN_BAND: |
| 719 | *slave_config |= ESPI_SLAVE_ALERT_MODE_IO1; |
| 720 | return; |
| 721 | case ESPI_ALERT_PIN_PUSH_PULL: |
| 722 | *slave_config |= ESPI_SLAVE_ALERT_MODE_PIN | ESPI_SLAVE_PUSH_PULL_ALERT_SEL; |
| 723 | *ctrlr_config |= ESPI_ALERT_MODE; |
| 724 | return; |
| 725 | case ESPI_ALERT_PIN_OPEN_DRAIN: |
| 726 | if (!(slave_caps & ESPI_SLAVE_OPEN_DRAIN_ALERT_SUPP)) |
| 727 | die("eSPI peripheral does not support open drain alert!"); |
| 728 | |
| 729 | *slave_config |= ESPI_SLAVE_ALERT_MODE_PIN | ESPI_SLAVE_OPEN_DRAIN_ALERT_SEL; |
| 730 | *ctrlr_config |= ESPI_ALERT_MODE; |
| 731 | return; |
| 732 | default: |
| 733 | die("Unknown espi alert config: %u!\n", alert_pin); |
| 734 | } |
| 735 | } |
| 736 | |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 737 | static int espi_set_general_configuration(const struct espi_config *mb_cfg, uint32_t slave_caps) |
| 738 | { |
| 739 | uint32_t slave_config = 0; |
| 740 | uint32_t ctrlr_config = 0; |
| 741 | |
| 742 | if (mb_cfg->crc_check_enable) { |
| 743 | slave_config |= ESPI_SLAVE_CRC_ENABLE; |
| 744 | ctrlr_config |= ESPI_CRC_CHECKING_EN; |
| 745 | } |
| 746 | |
Raul E Rangel | 8317e72 | 2021-05-05 13:38:27 -0600 | [diff] [blame] | 747 | espi_set_alert_pin_config(mb_cfg->alert_pin, slave_caps, &slave_config, &ctrlr_config); |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 748 | espi_set_io_mode_config(mb_cfg->io_mode, slave_caps, &slave_config, &ctrlr_config); |
| 749 | espi_set_op_freq_config(mb_cfg->op_freq_mhz, slave_caps, &slave_config, &ctrlr_config); |
| 750 | |
| 751 | if (CONFIG(ESPI_DEBUG)) |
| 752 | printk(BIOS_INFO, "Setting general configuration: slave: 0x%x controller: 0x%x\n", |
| 753 | slave_config, ctrlr_config); |
| 754 | |
Raul E Rangel | d2d762a | 2021-05-05 13:30:10 -0600 | [diff] [blame] | 755 | espi_show_slave_general_configuration(slave_config); |
| 756 | |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 757 | if (espi_set_configuration(ESPI_SLAVE_GENERAL_CFG, slave_config) == -1) |
| 758 | return -1; |
| 759 | |
| 760 | espi_write32(ESPI_SLAVE0_CONFIG, ctrlr_config); |
| 761 | return 0; |
| 762 | } |
| 763 | |
| 764 | static int espi_wait_channel_ready(uint16_t slave_reg_addr) |
| 765 | { |
| 766 | struct stopwatch sw; |
| 767 | uint32_t config; |
| 768 | |
| 769 | stopwatch_init_usecs_expire(&sw, ESPI_CH_READY_TIMEOUT_US); |
| 770 | do { |
| 771 | espi_get_configuration(slave_reg_addr, &config); |
| 772 | if (espi_slave_is_channel_ready(config)) |
| 773 | return 0; |
| 774 | } while (!stopwatch_expired(&sw)); |
| 775 | |
| 776 | printk(BIOS_ERR, "Error: Channel is not ready after %d usec (slave addr: 0x%x)\n", |
| 777 | ESPI_CH_READY_TIMEOUT_US, slave_reg_addr); |
| 778 | return -1; |
| 779 | |
| 780 | } |
| 781 | |
| 782 | static void espi_enable_ctrlr_channel(uint32_t channel_en) |
| 783 | { |
| 784 | uint32_t reg = espi_read32(ESPI_SLAVE0_CONFIG); |
| 785 | |
| 786 | reg |= channel_en; |
| 787 | |
| 788 | espi_write32(ESPI_SLAVE0_CONFIG, reg); |
| 789 | } |
| 790 | |
| 791 | static int espi_set_channel_configuration(uint32_t slave_config, uint32_t slave_reg_addr, |
| 792 | uint32_t ctrlr_enable) |
| 793 | { |
| 794 | if (espi_set_configuration(slave_reg_addr, slave_config) == -1) |
| 795 | return -1; |
| 796 | |
| 797 | if (!(slave_config & ESPI_SLAVE_CHANNEL_ENABLE)) |
| 798 | return 0; |
| 799 | |
| 800 | if (espi_wait_channel_ready(slave_reg_addr) == -1) |
| 801 | return -1; |
| 802 | |
| 803 | espi_enable_ctrlr_channel(ctrlr_enable); |
| 804 | return 0; |
| 805 | } |
| 806 | |
| 807 | static int espi_setup_vw_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) |
| 808 | { |
| 809 | uint32_t slave_vw_caps; |
| 810 | uint32_t ctrlr_vw_caps; |
| 811 | uint32_t slave_vw_count_supp; |
| 812 | uint32_t ctrlr_vw_count_supp; |
| 813 | uint32_t use_vw_count; |
| 814 | uint32_t slave_config; |
| 815 | |
| 816 | if (!mb_cfg->vw_ch_en) |
| 817 | return 0; |
| 818 | |
| 819 | if (!espi_slave_supports_vw_channel(slave_caps)) { |
| 820 | printk(BIOS_ERR, "Error: eSPI slave doesn't support VW channel!\n"); |
| 821 | return -1; |
| 822 | } |
| 823 | |
| 824 | if (espi_get_configuration(ESPI_SLAVE_VW_CFG, &slave_vw_caps) == -1) |
| 825 | return -1; |
| 826 | |
| 827 | ctrlr_vw_caps = espi_read32(ESPI_MASTER_CAP); |
| 828 | ctrlr_vw_count_supp = (ctrlr_vw_caps & ESPI_VW_MAX_SIZE_MASK) >> ESPI_VW_MAX_SIZE_SHIFT; |
| 829 | |
| 830 | slave_vw_count_supp = espi_slave_get_vw_count_supp(slave_vw_caps); |
| 831 | use_vw_count = MIN(ctrlr_vw_count_supp, slave_vw_count_supp); |
| 832 | |
| 833 | slave_config = ESPI_SLAVE_CHANNEL_ENABLE | ESPI_SLAVE_VW_COUNT_SEL_VAL(use_vw_count); |
| 834 | return espi_set_channel_configuration(slave_config, ESPI_SLAVE_VW_CFG, ESPI_VW_CH_EN); |
| 835 | } |
| 836 | |
| 837 | static int espi_setup_periph_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) |
| 838 | { |
| 839 | uint32_t slave_config; |
| 840 | /* Peripheral channel requires BME bit to be set when enabling the channel. */ |
| 841 | const uint32_t slave_en_mask = ESPI_SLAVE_CHANNEL_READY | |
| 842 | ESPI_SLAVE_PERIPH_BUS_MASTER_ENABLE; |
| 843 | |
| 844 | if (espi_get_configuration(ESPI_SLAVE_PERIPH_CFG, &slave_config) == -1) |
| 845 | return -1; |
| 846 | |
| 847 | /* |
| 848 | * Peripheral channel is the only one which is enabled on reset. So, if the mainboard |
| 849 | * wants to disable it, set configuration to disable peripheral channel. It also |
| 850 | * requires that BME bit be cleared. |
| 851 | */ |
| 852 | if (mb_cfg->periph_ch_en) { |
| 853 | if (!espi_slave_supports_periph_channel(slave_caps)) { |
| 854 | printk(BIOS_ERR, "Error: eSPI slave doesn't support periph channel!\n"); |
| 855 | return -1; |
| 856 | } |
| 857 | slave_config |= slave_en_mask; |
| 858 | } else { |
| 859 | slave_config &= ~slave_en_mask; |
| 860 | } |
| 861 | |
Raul E Rangel | 7222f7e | 2021-04-09 14:15:42 -0600 | [diff] [blame] | 862 | espi_show_slave_peripheral_channel_configuration(slave_config); |
| 863 | |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 864 | return espi_set_channel_configuration(slave_config, ESPI_SLAVE_PERIPH_CFG, |
| 865 | ESPI_PERIPH_CH_EN); |
| 866 | } |
| 867 | |
| 868 | static int espi_setup_oob_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) |
| 869 | { |
| 870 | uint32_t slave_config; |
| 871 | |
| 872 | if (!mb_cfg->oob_ch_en) |
| 873 | return 0; |
| 874 | |
| 875 | if (!espi_slave_supports_oob_channel(slave_caps)) { |
| 876 | printk(BIOS_ERR, "Error: eSPI slave doesn't support OOB channel!\n"); |
| 877 | return -1; |
| 878 | } |
| 879 | |
| 880 | if (espi_get_configuration(ESPI_SLAVE_OOB_CFG, &slave_config) == -1) |
| 881 | return -1; |
| 882 | |
| 883 | slave_config |= ESPI_SLAVE_CHANNEL_ENABLE; |
| 884 | |
| 885 | return espi_set_channel_configuration(slave_config, ESPI_SLAVE_OOB_CFG, |
| 886 | ESPI_OOB_CH_EN); |
| 887 | } |
| 888 | |
| 889 | static int espi_setup_flash_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) |
| 890 | { |
| 891 | uint32_t slave_config; |
| 892 | |
| 893 | if (!mb_cfg->flash_ch_en) |
| 894 | return 0; |
| 895 | |
| 896 | if (!espi_slave_supports_flash_channel(slave_caps)) { |
| 897 | printk(BIOS_ERR, "Error: eSPI slave doesn't support flash channel!\n"); |
| 898 | return -1; |
| 899 | } |
| 900 | |
| 901 | if (espi_get_configuration(ESPI_SLAVE_FLASH_CFG, &slave_config) == -1) |
| 902 | return -1; |
| 903 | |
| 904 | slave_config |= ESPI_SLAVE_CHANNEL_ENABLE; |
| 905 | |
| 906 | return espi_set_channel_configuration(slave_config, ESPI_SLAVE_FLASH_CFG, |
| 907 | ESPI_FLASH_CH_EN); |
| 908 | } |
| 909 | |
| 910 | static void espi_set_initial_config(const struct espi_config *mb_cfg) |
| 911 | { |
| 912 | uint32_t espi_initial_mode = ESPI_OP_FREQ_16_MHZ | ESPI_IO_MODE_SINGLE; |
| 913 | |
Raul E Rangel | dcec409 | 2021-05-07 15:35:10 -0600 | [diff] [blame] | 914 | switch (mb_cfg->alert_pin) { |
| 915 | case ESPI_ALERT_PIN_IN_BAND: |
| 916 | break; |
| 917 | case ESPI_ALERT_PIN_PUSH_PULL: |
| 918 | case ESPI_ALERT_PIN_OPEN_DRAIN: |
| 919 | espi_initial_mode |= ESPI_ALERT_MODE; |
| 920 | break; |
| 921 | default: |
| 922 | die("Unknown espi alert config: %u!\n", mb_cfg->alert_pin); |
| 923 | } |
| 924 | |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 925 | espi_write32(ESPI_SLAVE0_CONFIG, espi_initial_mode); |
| 926 | } |
| 927 | |
| 928 | static void espi_setup_subtractive_decode(const struct espi_config *mb_cfg) |
| 929 | { |
| 930 | uint32_t global_ctrl_reg; |
| 931 | global_ctrl_reg = espi_read32(ESPI_GLOBAL_CONTROL_1); |
| 932 | |
| 933 | if (mb_cfg->subtractive_decode) { |
| 934 | global_ctrl_reg &= ~ESPI_SUB_DECODE_SLV_MASK; |
| 935 | global_ctrl_reg |= ESPI_SUB_DECODE_EN; |
| 936 | |
| 937 | } else { |
| 938 | global_ctrl_reg &= ~ESPI_SUB_DECODE_EN; |
| 939 | } |
| 940 | espi_write32(ESPI_GLOBAL_CONTROL_1, global_ctrl_reg); |
| 941 | } |
| 942 | |
| 943 | int espi_setup(void) |
| 944 | { |
| 945 | uint32_t slave_caps; |
| 946 | const struct espi_config *cfg = espi_get_config(); |
| 947 | |
Martin Roth | 7a2bfeb | 2021-05-14 10:57:31 -0600 | [diff] [blame] | 948 | printk(BIOS_SPEW, "Initializing ESPI.\n"); |
| 949 | |
Raul E Rangel | b92383a | 2021-04-02 10:32:03 -0600 | [diff] [blame] | 950 | espi_write32(ESPI_GLOBAL_CONTROL_0, ESPI_AL_STOP_EN); |
| 951 | espi_write32(ESPI_GLOBAL_CONTROL_1, ESPI_RGCMD_INT(23) | ESPI_ERR_INT_SMI); |
| 952 | espi_write32(ESPI_SLAVE0_INT_EN, 0); |
| 953 | espi_clear_status(); |
Raul E Rangel | b95f848 | 2021-04-02 13:47:09 -0600 | [diff] [blame] | 954 | espi_clear_decodes(); |
Raul E Rangel | b92383a | 2021-04-02 10:32:03 -0600 | [diff] [blame] | 955 | |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 956 | /* |
| 957 | * Boot sequence: Step 1 |
| 958 | * Set correct initial configuration to talk to the slave: |
| 959 | * Set clock frequency to 16.7MHz and single IO mode. |
| 960 | */ |
| 961 | espi_set_initial_config(cfg); |
| 962 | |
| 963 | /* |
| 964 | * Boot sequence: Step 2 |
| 965 | * Send in-band reset |
| 966 | * The resets affects both host and slave devices, so set initial config again. |
| 967 | */ |
| 968 | if (espi_send_reset() == -1) { |
| 969 | printk(BIOS_ERR, "Error: In-band reset failed!\n"); |
| 970 | return -1; |
| 971 | } |
| 972 | espi_set_initial_config(cfg); |
| 973 | |
| 974 | /* |
| 975 | * Boot sequence: Step 3 |
| 976 | * Get configuration of slave device. |
| 977 | */ |
| 978 | if (espi_get_general_configuration(&slave_caps) == -1) { |
| 979 | printk(BIOS_ERR, "Error: Slave GET_CONFIGURATION failed!\n"); |
| 980 | return -1; |
| 981 | } |
| 982 | |
| 983 | /* |
| 984 | * Boot sequence: |
| 985 | * Step 4: Write slave device general config |
| 986 | * Step 5: Set host slave config |
| 987 | */ |
| 988 | if (espi_set_general_configuration(cfg, slave_caps) == -1) { |
| 989 | printk(BIOS_ERR, "Error: Slave SET_CONFIGURATION failed!\n"); |
| 990 | return -1; |
| 991 | } |
| 992 | |
| 993 | /* |
| 994 | * Setup polarity before enabling the VW channel so any interrupts |
| 995 | * received will have the correct polarity. |
| 996 | */ |
| 997 | espi_write32(ESPI_RXVW_POLARITY, cfg->vw_irq_polarity); |
| 998 | |
| 999 | /* |
| 1000 | * Boot Sequences: Steps 6 - 9 |
| 1001 | * Channel setup |
| 1002 | */ |
| 1003 | /* Set up VW first so we can deassert PLTRST#. */ |
| 1004 | if (espi_setup_vw_channel(cfg, slave_caps) == -1) { |
| 1005 | printk(BIOS_ERR, "Error: Setup VW channel failed!\n"); |
| 1006 | return -1; |
| 1007 | } |
| 1008 | |
| 1009 | /* De-assert PLTRST# if VW channel is enabled by mainboard. */ |
| 1010 | if (espi_send_pltrst_deassert(cfg) == -1) { |
| 1011 | printk(BIOS_ERR, "Error: PLTRST deassertion failed!\n"); |
| 1012 | return -1; |
| 1013 | } |
| 1014 | |
| 1015 | if (espi_setup_periph_channel(cfg, slave_caps) == -1) { |
| 1016 | printk(BIOS_ERR, "Error: Setup Periph channel failed!\n"); |
| 1017 | return -1; |
| 1018 | } |
| 1019 | |
| 1020 | if (espi_setup_oob_channel(cfg, slave_caps) == -1) { |
| 1021 | printk(BIOS_ERR, "Error: Setup OOB channel failed!\n"); |
| 1022 | return -1; |
| 1023 | } |
| 1024 | |
| 1025 | if (espi_setup_flash_channel(cfg, slave_caps) == -1) { |
| 1026 | printk(BIOS_ERR, "Error: Setup Flash channel failed!\n"); |
| 1027 | return -1; |
| 1028 | } |
| 1029 | |
Raul E Rangel | 61ac1bc | 2021-04-02 10:55:27 -0600 | [diff] [blame] | 1030 | if (espi_configure_decodes(cfg) == -1) { |
| 1031 | printk(BIOS_ERR, "Error: Configuring decodes failed!\n"); |
| 1032 | return -1; |
| 1033 | } |
| 1034 | |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 1035 | /* Enable subtractive decode if configured */ |
Felix Held | a2642d0 | 2021-02-17 00:32:46 +0100 | [diff] [blame] | 1036 | espi_setup_subtractive_decode(cfg); |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 1037 | |
Raul E Rangel | b92383a | 2021-04-02 10:32:03 -0600 | [diff] [blame] | 1038 | espi_write32(ESPI_GLOBAL_CONTROL_1, |
| 1039 | espi_read32(ESPI_GLOBAL_CONTROL_1) | ESPI_BUS_MASTER_EN); |
| 1040 | |
Martin Roth | 7a2bfeb | 2021-05-14 10:57:31 -0600 | [diff] [blame] | 1041 | printk(BIOS_SPEW, "Finished initializing ESPI.\n"); |
| 1042 | |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 1043 | return 0; |
| 1044 | } |