soc/amd/common/espi: Add ESPI_ prefix to SLAVE0_INT_EN
This matches the other register definitions.
BUG=b:183524609
TEST=Build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0ed92add633f294f92c6a0dde32851d01b10db3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c
index 152cdd9..45fcc6f 100644
--- a/src/soc/amd/common/block/lpc/espi_util.c
+++ b/src/soc/amd/common/block/lpc/espi_util.c
@@ -337,7 +337,7 @@
#define ESPI_SUB_DECODE_SLV_MASK (0x3 << ESPI_SUB_DECODE_SLV_SHIFT)
#define ESPI_SUB_DECODE_EN (1 << 2)
-#define SLAVE0_INT_STS 0x70
+#define ESPI_SLAVE0_INT_STS 0x70
#define ESPI_STATUS_DNCMD_COMPLETE (1 << 28)
#define ESPI_STATUS_NON_FATAL_ERROR (1 << 6)
#define ESPI_STATUS_FATAL_ERROR (1 << 5)
@@ -418,9 +418,9 @@
/* Clear interrupt status register */
static void espi_clear_status(void)
{
- uint32_t status = espi_read32(SLAVE0_INT_STS);
+ uint32_t status = espi_read32(ESPI_SLAVE0_INT_STS);
if (status)
- espi_write32(SLAVE0_INT_STS, status);
+ espi_write32(ESPI_SLAVE0_INT_STS, status);
}
/*
@@ -433,7 +433,7 @@
stopwatch_init_usecs_expire(&sw, ESPI_CMD_TIMEOUT_US);
do {
- *status = espi_read32(SLAVE0_INT_STS);
+ *status = espi_read32(ESPI_SLAVE0_INT_STS);
if (*status)
return 0;
} while (!stopwatch_expired(&sw));