Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 2 | |
| 3 | #include <amdblocks/chip.h> |
| 4 | #include <amdblocks/espi.h> |
| 5 | #include <amdblocks/lpc.h> |
| 6 | #include <arch/mmio.h> |
| 7 | #include <console/console.h> |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 8 | #include <espi.h> |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 9 | #include <soc/pci_devs.h> |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 10 | #include <timer.h> |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 11 | #include <types.h> |
| 12 | |
Furquan Shaikh | 98bc961 | 2020-05-09 19:31:55 -0700 | [diff] [blame] | 13 | static uintptr_t espi_bar; |
| 14 | |
| 15 | void espi_update_static_bar(uintptr_t bar) |
| 16 | { |
| 17 | espi_bar = bar; |
| 18 | } |
| 19 | |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 20 | static uintptr_t espi_get_bar(void) |
| 21 | { |
Martin Roth | b39e10d | 2020-07-14 11:08:55 -0600 | [diff] [blame] | 22 | if (ENV_X86 && !espi_bar) |
| 23 | espi_update_static_bar(lpc_get_spibase() + ESPI_OFFSET_FROM_BAR); |
Furquan Shaikh | 98bc961 | 2020-05-09 19:31:55 -0700 | [diff] [blame] | 24 | return espi_bar; |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 25 | } |
| 26 | |
Felix Held | 92dd678 | 2020-08-10 20:27:58 +0200 | [diff] [blame^] | 27 | static uint32_t espi_read32(unsigned int reg) |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 28 | { |
| 29 | return read32((void *)(espi_get_bar() + reg)); |
| 30 | } |
| 31 | |
Felix Held | 92dd678 | 2020-08-10 20:27:58 +0200 | [diff] [blame^] | 32 | static void espi_write32(unsigned int reg, uint32_t val) |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 33 | { |
| 34 | write32((void *)(espi_get_bar() + reg), val); |
| 35 | } |
| 36 | |
Felix Held | 92dd678 | 2020-08-10 20:27:58 +0200 | [diff] [blame^] | 37 | static uint16_t espi_read16(unsigned int reg) |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 38 | { |
| 39 | return read16((void *)(espi_get_bar() + reg)); |
| 40 | } |
| 41 | |
Felix Held | 92dd678 | 2020-08-10 20:27:58 +0200 | [diff] [blame^] | 42 | static void espi_write16(unsigned int reg, uint16_t val) |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 43 | { |
| 44 | write16((void *)(espi_get_bar() + reg), val); |
| 45 | } |
| 46 | |
Felix Held | 92dd678 | 2020-08-10 20:27:58 +0200 | [diff] [blame^] | 47 | static uint8_t espi_read8(unsigned int reg) |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 48 | { |
| 49 | return read8((void *)(espi_get_bar() + reg)); |
| 50 | } |
| 51 | |
Felix Held | 92dd678 | 2020-08-10 20:27:58 +0200 | [diff] [blame^] | 52 | static void espi_write8(unsigned int reg, uint8_t val) |
Furquan Shaikh | f318e03 | 2020-05-04 23:38:53 -0700 | [diff] [blame] | 53 | { |
| 54 | write8((void *)(espi_get_bar() + reg), val); |
| 55 | } |
| 56 | |
| 57 | static void espi_enable_decode(int decode_en) |
| 58 | { |
| 59 | uint32_t val; |
| 60 | |
| 61 | val = espi_read32(ESPI_DECODE); |
| 62 | val |= decode_en; |
| 63 | espi_write32(ESPI_DECODE, val); |
| 64 | } |
| 65 | |
| 66 | static bool espi_is_decode_enabled(int decode) |
| 67 | { |
| 68 | uint32_t val; |
| 69 | |
| 70 | val = espi_read32(ESPI_DECODE); |
| 71 | return !!(val & decode); |
| 72 | } |
| 73 | |
| 74 | static int espi_find_io_window(uint16_t win_base) |
| 75 | { |
| 76 | int i; |
| 77 | |
| 78 | for (i = 0; i < ESPI_GENERIC_IO_WIN_COUNT; i++) { |
| 79 | if (!espi_is_decode_enabled(ESPI_DECODE_IO_RANGE_EN(i))) |
| 80 | continue; |
| 81 | |
| 82 | if (espi_read16(ESPI_IO_RANGE_BASE(i)) == win_base) |
| 83 | return i; |
| 84 | } |
| 85 | |
| 86 | return -1; |
| 87 | } |
| 88 | |
| 89 | static int espi_get_unused_io_window(void) |
| 90 | { |
| 91 | int i; |
| 92 | |
| 93 | for (i = 0; i < ESPI_GENERIC_IO_WIN_COUNT; i++) { |
| 94 | if (!espi_is_decode_enabled(ESPI_DECODE_IO_RANGE_EN(i))) |
| 95 | return i; |
| 96 | } |
| 97 | |
| 98 | return -1; |
| 99 | } |
| 100 | |
| 101 | /* |
| 102 | * Returns decode enable bits for standard IO port addresses. If port address is not supported |
| 103 | * by standard decode or if the size of window is not 1, then it returns -1. |
| 104 | */ |
| 105 | static int espi_std_io_decode(uint16_t base, size_t size) |
| 106 | { |
| 107 | int ret = -1; |
| 108 | |
| 109 | if (size != 1) |
| 110 | return ret; |
| 111 | |
| 112 | switch (base) { |
| 113 | case 0x80: |
| 114 | ret = ESPI_DECODE_IO_0x80_EN; |
| 115 | break; |
| 116 | case 0x60: |
| 117 | case 0x64: |
| 118 | ret = ESPI_DECODE_IO_0X60_0X64_EN; |
| 119 | break; |
| 120 | case 0x2e: |
| 121 | case 0x2f: |
| 122 | ret = ESPI_DECODE_IO_0X2E_0X2F_EN; |
| 123 | break; |
| 124 | default: |
| 125 | ret = -1; |
| 126 | break; |
| 127 | } |
| 128 | |
| 129 | return ret; |
| 130 | } |
| 131 | |
| 132 | static size_t espi_get_io_window_size(int idx) |
| 133 | { |
| 134 | return espi_read8(ESPI_IO_RANGE_SIZE(idx)) + 1; |
| 135 | } |
| 136 | |
| 137 | static void espi_write_io_window(int idx, uint16_t base, size_t size) |
| 138 | { |
| 139 | espi_write16(ESPI_IO_RANGE_BASE(idx), base); |
| 140 | espi_write8(ESPI_IO_RANGE_SIZE(idx), size - 1); |
| 141 | } |
| 142 | |
| 143 | static int espi_open_generic_io_window(uint16_t base, size_t size) |
| 144 | { |
| 145 | size_t win_size; |
| 146 | int idx; |
| 147 | |
| 148 | for (; size; size -= win_size, base += win_size) { |
| 149 | win_size = MIN(size, ESPI_GENERIC_IO_MAX_WIN_SIZE); |
| 150 | |
| 151 | idx = espi_find_io_window(base); |
| 152 | if (idx != -1) { |
| 153 | size_t curr_size = espi_get_io_window_size(idx); |
| 154 | |
| 155 | if (curr_size > win_size) { |
| 156 | printk(BIOS_INFO, "eSPI window already configured to be larger than requested! "); |
| 157 | printk(BIOS_INFO, "Base: 0x%x, Requested size: 0x%zx, Actual size: 0x%zx\n", |
| 158 | base, win_size, curr_size); |
| 159 | } else if (curr_size < win_size) { |
| 160 | espi_write_io_window(idx, base, win_size); |
| 161 | printk(BIOS_INFO, "eSPI window at base: 0x%x resized from 0x%zx to 0x%zx\n", |
| 162 | base, curr_size, win_size); |
| 163 | } |
| 164 | |
| 165 | continue; |
| 166 | } |
| 167 | |
| 168 | idx = espi_get_unused_io_window(); |
| 169 | if (idx == -1) { |
| 170 | printk(BIOS_ERR, "Cannot open IO window base %x size %zx\n", base, |
| 171 | size); |
| 172 | printk(BIOS_ERR, "ERROR: No more available IO windows!\n"); |
| 173 | return -1; |
| 174 | } |
| 175 | |
| 176 | espi_write_io_window(idx, base, win_size); |
| 177 | espi_enable_decode(ESPI_DECODE_IO_RANGE_EN(idx)); |
| 178 | } |
| 179 | |
| 180 | return 0; |
| 181 | } |
| 182 | |
| 183 | int espi_open_io_window(uint16_t base, size_t size) |
| 184 | { |
| 185 | int std_io; |
| 186 | |
| 187 | std_io = espi_std_io_decode(base, size); |
| 188 | if (std_io != -1) { |
| 189 | espi_enable_decode(std_io); |
| 190 | return 0; |
| 191 | } |
| 192 | |
| 193 | return espi_open_generic_io_window(base, size); |
| 194 | } |
| 195 | |
| 196 | static int espi_find_mmio_window(uint32_t win_base) |
| 197 | { |
| 198 | int i; |
| 199 | |
| 200 | for (i = 0; i < ESPI_GENERIC_MMIO_WIN_COUNT; i++) { |
| 201 | if (!espi_is_decode_enabled(ESPI_DECODE_MMIO_RANGE_EN(i))) |
| 202 | continue; |
| 203 | |
| 204 | if (espi_read32(ESPI_MMIO_RANGE_BASE(i)) == win_base) |
| 205 | return i; |
| 206 | } |
| 207 | |
| 208 | return -1; |
| 209 | } |
| 210 | |
| 211 | static int espi_get_unused_mmio_window(void) |
| 212 | { |
| 213 | int i; |
| 214 | |
| 215 | for (i = 0; i < ESPI_GENERIC_MMIO_WIN_COUNT; i++) { |
| 216 | if (!espi_is_decode_enabled(ESPI_DECODE_MMIO_RANGE_EN(i))) |
| 217 | return i; |
| 218 | } |
| 219 | |
| 220 | return -1; |
| 221 | |
| 222 | } |
| 223 | |
| 224 | static size_t espi_get_mmio_window_size(int idx) |
| 225 | { |
| 226 | return espi_read16(ESPI_MMIO_RANGE_SIZE(idx)) + 1; |
| 227 | } |
| 228 | |
| 229 | static void espi_write_mmio_window(int idx, uint32_t base, size_t size) |
| 230 | { |
| 231 | espi_write32(ESPI_MMIO_RANGE_BASE(idx), base); |
| 232 | espi_write16(ESPI_MMIO_RANGE_SIZE(idx), size - 1); |
| 233 | } |
| 234 | |
| 235 | int espi_open_mmio_window(uint32_t base, size_t size) |
| 236 | { |
| 237 | size_t win_size; |
| 238 | int idx; |
| 239 | |
| 240 | for (; size; size -= win_size, base += win_size) { |
| 241 | win_size = MIN(size, ESPI_GENERIC_MMIO_MAX_WIN_SIZE); |
| 242 | |
| 243 | idx = espi_find_mmio_window(base); |
| 244 | if (idx != -1) { |
| 245 | size_t curr_size = espi_get_mmio_window_size(idx); |
| 246 | |
| 247 | if (curr_size > win_size) { |
| 248 | printk(BIOS_INFO, "eSPI window already configured to be larger than requested! "); |
| 249 | printk(BIOS_INFO, "Base: 0x%x, Requested size: 0x%zx, Actual size: 0x%zx\n", |
| 250 | base, win_size, curr_size); |
| 251 | } else if (curr_size < win_size) { |
| 252 | espi_write_mmio_window(idx, base, win_size); |
| 253 | printk(BIOS_INFO, "eSPI window at base: 0x%x resized from 0x%zx to 0x%zx\n", |
| 254 | base, curr_size, win_size); |
| 255 | } |
| 256 | |
| 257 | continue; |
| 258 | } |
| 259 | |
| 260 | idx = espi_get_unused_mmio_window(); |
| 261 | if (idx == -1) { |
| 262 | printk(BIOS_ERR, "Cannot open IO window base %x size %zx\n", base, |
| 263 | size); |
| 264 | printk(BIOS_ERR, "ERROR: No more available MMIO windows!\n"); |
| 265 | return -1; |
| 266 | } |
| 267 | |
| 268 | espi_write_mmio_window(idx, base, win_size); |
| 269 | espi_enable_decode(ESPI_DECODE_MMIO_RANGE_EN(idx)); |
| 270 | } |
| 271 | |
| 272 | return 0; |
| 273 | } |
| 274 | |
| 275 | static const struct espi_config *espi_get_config(void) |
| 276 | { |
| 277 | const struct soc_amd_common_config *soc_cfg = soc_get_common_config(); |
| 278 | |
| 279 | if (!soc_cfg) |
| 280 | die("Common config structure is NULL!\n"); |
| 281 | |
| 282 | return &soc_cfg->espi_config; |
| 283 | } |
| 284 | |
| 285 | void espi_configure_decodes(void) |
| 286 | { |
| 287 | int i; |
| 288 | const struct espi_config *cfg = espi_get_config(); |
| 289 | |
| 290 | espi_enable_decode(cfg->std_io_decode_bitmap); |
| 291 | |
| 292 | for (i = 0; i < ESPI_GENERIC_IO_WIN_COUNT; i++) { |
| 293 | if (cfg->generic_io_range[i].size == 0) |
| 294 | continue; |
| 295 | espi_open_generic_io_window(cfg->generic_io_range[i].base, |
| 296 | cfg->generic_io_range[i].size); |
| 297 | } |
| 298 | } |
Furquan Shaikh | 70063ff5 | 2020-05-11 14:28:13 -0700 | [diff] [blame] | 299 | |
| 300 | #define ESPI_DN_TX_HDR0 0x00 |
| 301 | enum espi_cmd_type { |
| 302 | CMD_TYPE_SET_CONFIGURATION = 0, |
| 303 | CMD_TYPE_GET_CONFIGURATION = 1, |
| 304 | CMD_TYPE_IN_BAND_RESET = 2, |
| 305 | CMD_TYPE_PERIPHERAL = 4, |
| 306 | CMD_TYPE_VW = 5, |
| 307 | CMD_TYPE_OOB = 6, |
| 308 | CMD_TYPE_FLASH = 7, |
| 309 | }; |
| 310 | |
| 311 | #define ESPI_DN_TX_HDR1 0x04 |
| 312 | #define ESPI_DN_TX_HDR2 0x08 |
| 313 | #define ESPI_DN_TX_DATA 0x0c |
| 314 | |
| 315 | #define ESPI_MASTER_CAP 0x2c |
| 316 | #define ESPI_VW_MAX_SIZE_SHIFT 13 |
| 317 | #define ESPI_VW_MAX_SIZE_MASK (0x3f << ESPI_VW_MAX_SIZE_SHIFT) |
| 318 | |
| 319 | #define ESPI_GLOBAL_CONTROL_1 0x34 |
| 320 | #define ESPI_SUB_DECODE_SLV_SHIFT 3 |
| 321 | #define ESPI_SUB_DECODE_SLV_MASK (0x3 << ESPI_SUB_DECODE_SLV_SHIFT) |
| 322 | #define ESPI_SUB_DECODE_EN (1 << 2) |
| 323 | |
| 324 | #define SLAVE0_INT_STS 0x70 |
| 325 | #define ESPI_STATUS_DNCMD_COMPLETE (1 << 28) |
| 326 | #define ESPI_STATUS_NON_FATAL_ERROR (1 << 6) |
| 327 | #define ESPI_STATUS_FATAL_ERROR (1 << 5) |
| 328 | #define ESPI_STATUS_NO_RESPONSE (1 << 4) |
| 329 | #define ESPI_STATUS_CRC_ERR (1 << 2) |
| 330 | #define ESPI_STATUS_WAIT_TIMEOUT (1 << 1) |
| 331 | #define ESPI_STATUS_BUS_ERROR (1 << 0) |
| 332 | |
| 333 | #define ESPI_RXVW_POLARITY 0xac |
| 334 | |
| 335 | #define ESPI_CMD_TIMEOUT_US 100 |
| 336 | #define ESPI_CH_READY_TIMEOUT_US 1000 |
| 337 | |
| 338 | union espi_txhdr0 { |
| 339 | uint32_t val; |
| 340 | struct { |
| 341 | uint32_t cmd_type:3; |
| 342 | uint32_t cmd_sts:1; |
| 343 | uint32_t slave_sel:2; |
| 344 | uint32_t rsvd:2; |
| 345 | uint32_t hdata0:8; |
| 346 | uint32_t hdata1:8; |
| 347 | uint32_t hdata2:8; |
| 348 | }; |
| 349 | } __packed; |
| 350 | |
| 351 | union espi_txhdr1 { |
| 352 | uint32_t val; |
| 353 | struct { |
| 354 | uint32_t hdata3:8; |
| 355 | uint32_t hdata4:8; |
| 356 | uint32_t hdata5:8; |
| 357 | uint32_t hdata6:8; |
| 358 | }; |
| 359 | } __packed; |
| 360 | |
| 361 | union espi_txhdr2 { |
| 362 | uint32_t val; |
| 363 | struct { |
| 364 | uint32_t hdata7:8; |
| 365 | uint32_t rsvd:24; |
| 366 | }; |
| 367 | } __packed; |
| 368 | |
| 369 | union espi_txdata { |
| 370 | uint32_t val; |
| 371 | struct { |
| 372 | uint32_t byte0:8; |
| 373 | uint32_t byte1:8; |
| 374 | uint32_t byte2:8; |
| 375 | uint32_t byte3:8; |
| 376 | }; |
| 377 | } __packed; |
| 378 | |
| 379 | struct espi_cmd { |
| 380 | union espi_txhdr0 hdr0; |
| 381 | union espi_txhdr1 hdr1; |
| 382 | union espi_txhdr2 hdr2; |
| 383 | union espi_txdata data; |
| 384 | } __packed; |
| 385 | |
| 386 | /* Wait up to ESPI_CMD_TIMEOUT_US for hardware to clear DNCMD_STATUS bit. */ |
| 387 | static int espi_wait_ready(void) |
| 388 | { |
| 389 | struct stopwatch sw; |
| 390 | union espi_txhdr0 hdr0; |
| 391 | |
| 392 | stopwatch_init_usecs_expire(&sw, ESPI_CMD_TIMEOUT_US); |
| 393 | do { |
| 394 | hdr0.val = espi_read32(ESPI_DN_TX_HDR0); |
| 395 | if (!hdr0.cmd_sts) |
| 396 | return 0; |
| 397 | } while (!stopwatch_expired(&sw)); |
| 398 | |
| 399 | return -1; |
| 400 | } |
| 401 | |
| 402 | /* Clear interrupt status register */ |
| 403 | static void espi_clear_status(void) |
| 404 | { |
| 405 | uint32_t status = espi_read32(SLAVE0_INT_STS); |
| 406 | if (status) |
| 407 | espi_write32(SLAVE0_INT_STS, status); |
| 408 | } |
| 409 | |
| 410 | /* |
| 411 | * Wait up to ESPI_CMD_TIMEOUT_US for interrupt status register to update after sending a |
| 412 | * command. |
| 413 | */ |
| 414 | static int espi_check_status(uint32_t *status) |
| 415 | { |
| 416 | struct stopwatch sw; |
| 417 | |
| 418 | stopwatch_init_usecs_expire(&sw, ESPI_CMD_TIMEOUT_US); |
| 419 | do { |
| 420 | *status = espi_read32(SLAVE0_INT_STS); |
| 421 | if (*status) |
| 422 | return 0; |
| 423 | } while (!stopwatch_expired(&sw)); |
| 424 | |
| 425 | printk(BIOS_ERR, "Error: eSPI timed out waiting for status update.\n"); |
| 426 | |
| 427 | return -1; |
| 428 | } |
| 429 | |
| 430 | static void espi_show_failure(const struct espi_cmd *cmd, const char *str, uint32_t status) |
| 431 | { |
| 432 | printk(BIOS_ERR, "eSPI cmd0-cmd2: %08x %08x %08x data: %08x.\n", |
| 433 | cmd->hdr0.val, cmd->hdr1.val, cmd->hdr2.val, cmd->data.val); |
| 434 | printk(BIOS_ERR, "%s (Status = 0x%x)\n", str, status); |
| 435 | } |
| 436 | |
| 437 | static int espi_send_command(const struct espi_cmd *cmd) |
| 438 | { |
| 439 | uint32_t status; |
| 440 | |
| 441 | if (CONFIG(ESPI_DEBUG)) |
| 442 | printk(BIOS_ERR, "eSPI cmd0-cmd2: %08x %08x %08x data: %08x.\n", |
| 443 | cmd->hdr0.val, cmd->hdr1.val, cmd->hdr2.val, cmd->data.val); |
| 444 | |
| 445 | if (espi_wait_ready() == -1) { |
| 446 | espi_show_failure(cmd, "Error: eSPI was not ready to accept a command", 0); |
| 447 | return -1; |
| 448 | } |
| 449 | |
| 450 | espi_clear_status(); |
| 451 | |
| 452 | espi_write32(ESPI_DN_TX_HDR1, cmd->hdr1.val); |
| 453 | espi_write32(ESPI_DN_TX_HDR2, cmd->hdr2.val); |
| 454 | espi_write32(ESPI_DN_TX_DATA, cmd->data.val); |
| 455 | |
| 456 | /* Dword 0 must be last as this write triggers the transaction */ |
| 457 | espi_write32(ESPI_DN_TX_HDR0, cmd->hdr0.val); |
| 458 | |
| 459 | if (espi_wait_ready() == -1) { |
| 460 | espi_show_failure(cmd, |
| 461 | "Error: eSPI timed out waiting for command to complete", 0); |
| 462 | return -1; |
| 463 | } |
| 464 | |
| 465 | if (espi_check_status(&status) == -1) { |
| 466 | espi_show_failure(cmd, "Error: eSPI check status failed", 0); |
| 467 | return -1; |
| 468 | } |
| 469 | |
| 470 | /* If command did not complete downstream, return error. */ |
| 471 | if (!(status & ESPI_STATUS_DNCMD_COMPLETE)) { |
| 472 | espi_show_failure(cmd, "Error: eSPI downstream command completion failure", |
| 473 | status); |
| 474 | return -1; |
| 475 | } |
| 476 | |
| 477 | if (status & ~ESPI_STATUS_DNCMD_COMPLETE) { |
| 478 | espi_show_failure(cmd, "Error: eSPI status register bits set", status); |
| 479 | return -1; |
| 480 | } |
| 481 | |
| 482 | return 0; |
| 483 | } |
| 484 | |
| 485 | static int espi_send_reset(void) |
| 486 | { |
| 487 | struct espi_cmd cmd = { |
| 488 | .hdr0 = { |
| 489 | .cmd_type = CMD_TYPE_IN_BAND_RESET, |
| 490 | .cmd_sts = 1, |
| 491 | }, |
| 492 | }; |
| 493 | |
| 494 | return espi_send_command(&cmd); |
| 495 | } |
| 496 | |
| 497 | static int espi_send_pltrst_deassert(const struct espi_config *mb_cfg) |
| 498 | { |
| 499 | struct espi_cmd cmd = { |
| 500 | .hdr0 = { |
| 501 | .cmd_type = CMD_TYPE_VW, |
| 502 | .cmd_sts = 1, |
| 503 | .hdata0 = 0, /* 1 VW group */ |
| 504 | }, |
| 505 | .data = { |
| 506 | .byte0 = ESPI_VW_INDEX_SYSTEM_EVENT_3, |
| 507 | .byte1 = ESPI_VW_SIGNAL_HIGH(ESPI_VW_PLTRST), |
| 508 | }, |
| 509 | }; |
| 510 | |
| 511 | if (!mb_cfg->vw_ch_en) |
| 512 | return 0; |
| 513 | |
| 514 | return espi_send_command(&cmd); |
| 515 | } |
| 516 | |
| 517 | /* |
| 518 | * In case of get configuration command, hdata0 contains bits 15:8 of the slave register address |
| 519 | * and hdata1 contains bits 7:0 of the slave register address. |
| 520 | */ |
| 521 | #define ESPI_CONFIGURATION_HDATA0(a) (((a) >> 8) & 0xff) |
| 522 | #define ESPI_CONFIGURATION_HDATA1(a) ((a) & 0xff) |
| 523 | |
| 524 | static int espi_get_configuration(uint16_t slave_reg_addr, uint32_t *config) |
| 525 | { |
| 526 | struct espi_cmd cmd = { |
| 527 | .hdr0 = { |
| 528 | .cmd_type = CMD_TYPE_GET_CONFIGURATION, |
| 529 | .cmd_sts = 1, |
| 530 | .hdata0 = ESPI_CONFIGURATION_HDATA0(slave_reg_addr), |
| 531 | .hdata1 = ESPI_CONFIGURATION_HDATA1(slave_reg_addr), |
| 532 | }, |
| 533 | }; |
| 534 | |
| 535 | *config = 0; |
| 536 | |
| 537 | if (espi_send_command(&cmd)) |
| 538 | return -1; |
| 539 | |
| 540 | *config = espi_read32(ESPI_DN_TX_HDR1); |
| 541 | |
| 542 | if (CONFIG(ESPI_DEBUG)) |
| 543 | printk(BIOS_DEBUG, "Get configuration for slave register(0x%x): 0x%x\n", |
| 544 | slave_reg_addr, *config); |
| 545 | |
| 546 | return 0; |
| 547 | } |
| 548 | |
| 549 | static int espi_set_configuration(uint16_t slave_reg_addr, uint32_t config) |
| 550 | { |
| 551 | struct espi_cmd cmd = { |
| 552 | .hdr0 = { |
| 553 | .cmd_type = CMD_TYPE_SET_CONFIGURATION, |
| 554 | .cmd_sts = 1, |
| 555 | .hdata0 = ESPI_CONFIGURATION_HDATA0(slave_reg_addr), |
| 556 | .hdata1 = ESPI_CONFIGURATION_HDATA1(slave_reg_addr), |
| 557 | }, |
| 558 | .hdr1 = { |
| 559 | .val = config, |
| 560 | }, |
| 561 | }; |
| 562 | |
| 563 | return espi_send_command(&cmd); |
| 564 | } |
| 565 | |
| 566 | static int espi_get_general_configuration(uint32_t *config) |
| 567 | { |
| 568 | int ret = espi_get_configuration(ESPI_SLAVE_GENERAL_CFG, config); |
| 569 | if (ret == -1) |
| 570 | return -1; |
| 571 | |
| 572 | espi_show_slave_general_configuration(*config); |
| 573 | return 0; |
| 574 | } |
| 575 | |
| 576 | static void espi_set_io_mode_config(enum espi_io_mode mb_io_mode, uint32_t slave_caps, |
| 577 | uint32_t *slave_config, uint32_t *ctrlr_config) |
| 578 | { |
| 579 | switch (mb_io_mode) { |
| 580 | case ESPI_IO_MODE_QUAD: |
| 581 | if (espi_slave_supports_quad_io(slave_caps)) { |
| 582 | *slave_config |= ESPI_SLAVE_IO_MODE_SEL_QUAD; |
| 583 | *ctrlr_config |= ESPI_IO_MODE_QUAD; |
| 584 | break; |
| 585 | } |
| 586 | printk(BIOS_ERR, "Error: eSPI Quad I/O not supported. Dropping to dual mode.\n"); |
| 587 | /* Intentional fall-through */ |
| 588 | case ESPI_IO_MODE_DUAL: |
| 589 | if (espi_slave_supports_dual_io(slave_caps)) { |
| 590 | *slave_config |= ESPI_SLAVE_IO_MODE_SEL_DUAL; |
| 591 | *ctrlr_config |= ESPI_IO_MODE_DUAL; |
| 592 | break; |
| 593 | } |
| 594 | printk(BIOS_ERR, |
| 595 | "Error: eSPI Dual I/O not supported. Dropping to single mode.\n"); |
| 596 | /* Intentional fall-through */ |
| 597 | case ESPI_IO_MODE_SINGLE: |
| 598 | /* Single I/O mode is always supported. */ |
| 599 | *slave_config |= ESPI_SLAVE_IO_MODE_SEL_SINGLE; |
| 600 | *ctrlr_config |= ESPI_IO_MODE_SINGLE; |
| 601 | break; |
| 602 | default: |
| 603 | die("No supported eSPI I/O modes!\n"); |
| 604 | } |
| 605 | } |
| 606 | |
| 607 | static void espi_set_op_freq_config(enum espi_op_freq mb_op_freq, uint32_t slave_caps, |
| 608 | uint32_t *slave_config, uint32_t *ctrlr_config) |
| 609 | { |
| 610 | int slave_max_speed_mhz = espi_slave_max_speed_mhz_supported(slave_caps); |
| 611 | |
| 612 | switch (mb_op_freq) { |
| 613 | case ESPI_OP_FREQ_66_MHZ: |
| 614 | if (slave_max_speed_mhz >= 66) { |
| 615 | *slave_config |= ESPI_SLAVE_OP_FREQ_SEL_66_MHZ; |
| 616 | *ctrlr_config |= ESPI_OP_FREQ_66_MHZ; |
| 617 | break; |
| 618 | } |
| 619 | printk(BIOS_ERR, "Error: eSPI 66MHz not supported. Dropping to 33MHz.\n"); |
| 620 | /* Intentional fall-through */ |
| 621 | case ESPI_OP_FREQ_33_MHZ: |
| 622 | if (slave_max_speed_mhz >= 33) { |
| 623 | *slave_config |= ESPI_SLAVE_OP_FREQ_SEL_33_MHZ; |
| 624 | *ctrlr_config |= ESPI_OP_FREQ_33_MHZ; |
| 625 | break; |
| 626 | } |
| 627 | printk(BIOS_ERR, "Error: eSPI 33MHz not supported. Dropping to 16MHz.\n"); |
| 628 | /* Intentional fall-through */ |
| 629 | case ESPI_OP_FREQ_16_MHZ: |
| 630 | /* |
| 631 | * eSPI spec says the minimum frequency is 20MHz, but AMD datasheets support |
| 632 | * 16.7 Mhz. |
| 633 | */ |
| 634 | if (slave_max_speed_mhz > 0) { |
| 635 | *slave_config |= ESPI_SLAVE_OP_FREQ_SEL_20_MHZ; |
| 636 | *ctrlr_config |= ESPI_OP_FREQ_16_MHZ; |
| 637 | break; |
| 638 | } |
| 639 | /* Intentional fall-through */ |
| 640 | default: |
| 641 | die("No supported eSPI Operating Frequency!\n"); |
| 642 | } |
| 643 | } |
| 644 | |
| 645 | static int espi_set_general_configuration(const struct espi_config *mb_cfg, uint32_t slave_caps) |
| 646 | { |
| 647 | uint32_t slave_config = 0; |
| 648 | uint32_t ctrlr_config = 0; |
| 649 | |
| 650 | if (mb_cfg->crc_check_enable) { |
| 651 | slave_config |= ESPI_SLAVE_CRC_ENABLE; |
| 652 | ctrlr_config |= ESPI_CRC_CHECKING_EN; |
| 653 | } |
| 654 | |
| 655 | if (mb_cfg->dedicated_alert_pin) { |
| 656 | slave_config |= ESPI_SLAVE_ALERT_MODE_PIN; |
| 657 | ctrlr_config |= ESPI_ALERT_MODE; |
| 658 | } |
| 659 | |
| 660 | espi_set_io_mode_config(mb_cfg->io_mode, slave_caps, &slave_config, &ctrlr_config); |
| 661 | espi_set_op_freq_config(mb_cfg->op_freq_mhz, slave_caps, &slave_config, &ctrlr_config); |
| 662 | |
| 663 | if (CONFIG(ESPI_DEBUG)) |
| 664 | printk(BIOS_INFO, "Setting general configuration: slave: 0x%x controller: 0x%x\n", |
| 665 | slave_config, ctrlr_config); |
| 666 | |
| 667 | if (espi_set_configuration(ESPI_SLAVE_GENERAL_CFG, slave_config) == -1) |
| 668 | return -1; |
| 669 | |
| 670 | espi_write32(ESPI_SLAVE0_CONFIG, ctrlr_config); |
| 671 | return 0; |
| 672 | } |
| 673 | |
| 674 | static int espi_wait_channel_ready(uint16_t slave_reg_addr) |
| 675 | { |
| 676 | struct stopwatch sw; |
| 677 | uint32_t config; |
| 678 | |
| 679 | stopwatch_init_usecs_expire(&sw, ESPI_CH_READY_TIMEOUT_US); |
| 680 | do { |
| 681 | espi_get_configuration(slave_reg_addr, &config); |
| 682 | if (espi_slave_is_channel_ready(config)) |
| 683 | return 0; |
| 684 | } while (!stopwatch_expired(&sw)); |
| 685 | |
| 686 | printk(BIOS_ERR, "Error: Channel is not ready after %d usec (slave addr: 0x%x)\n", |
| 687 | ESPI_CH_READY_TIMEOUT_US, slave_reg_addr); |
| 688 | return -1; |
| 689 | |
| 690 | } |
| 691 | |
| 692 | static void espi_enable_ctrlr_channel(uint32_t channel_en) |
| 693 | { |
| 694 | uint32_t reg = espi_read32(ESPI_SLAVE0_CONFIG); |
| 695 | |
| 696 | reg |= channel_en; |
| 697 | |
| 698 | espi_write32(ESPI_SLAVE0_CONFIG, reg); |
| 699 | } |
| 700 | |
| 701 | static int espi_set_channel_configuration(uint32_t slave_config, uint32_t slave_reg_addr, |
| 702 | uint32_t ctrlr_enable) |
| 703 | { |
| 704 | if (espi_set_configuration(slave_reg_addr, slave_config) == -1) |
| 705 | return -1; |
| 706 | |
| 707 | if (!(slave_config & ESPI_SLAVE_CHANNEL_ENABLE)) |
| 708 | return 0; |
| 709 | |
| 710 | if (espi_wait_channel_ready(slave_reg_addr) == -1) |
| 711 | return -1; |
| 712 | |
| 713 | espi_enable_ctrlr_channel(ctrlr_enable); |
| 714 | return 0; |
| 715 | } |
| 716 | |
| 717 | static int espi_setup_vw_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) |
| 718 | { |
| 719 | uint32_t slave_vw_caps; |
| 720 | uint32_t ctrlr_vw_caps; |
| 721 | uint32_t slave_vw_count_supp; |
| 722 | uint32_t ctrlr_vw_count_supp; |
| 723 | uint32_t use_vw_count; |
| 724 | uint32_t slave_config; |
| 725 | |
| 726 | if (!mb_cfg->vw_ch_en) |
| 727 | return 0; |
| 728 | |
| 729 | if (!espi_slave_supports_vw_channel(slave_caps)) { |
| 730 | printk(BIOS_ERR, "Error: eSPI slave doesn't support VW channel!\n"); |
| 731 | return -1; |
| 732 | } |
| 733 | |
| 734 | if (espi_get_configuration(ESPI_SLAVE_VW_CFG, &slave_vw_caps) == -1) |
| 735 | return -1; |
| 736 | |
| 737 | ctrlr_vw_caps = espi_read32(ESPI_MASTER_CAP); |
| 738 | ctrlr_vw_count_supp = (ctrlr_vw_caps & ESPI_VW_MAX_SIZE_MASK) >> ESPI_VW_MAX_SIZE_SHIFT; |
| 739 | |
| 740 | slave_vw_count_supp = espi_slave_get_vw_count_supp(slave_vw_caps); |
| 741 | use_vw_count = MIN(ctrlr_vw_count_supp, slave_vw_count_supp); |
| 742 | |
| 743 | slave_config = ESPI_SLAVE_CHANNEL_ENABLE | ESPI_SLAVE_VW_COUNT_SEL_VAL(use_vw_count); |
| 744 | return espi_set_channel_configuration(slave_config, ESPI_SLAVE_VW_CFG, ESPI_VW_CH_EN); |
| 745 | } |
| 746 | |
| 747 | static int espi_setup_periph_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) |
| 748 | { |
| 749 | uint32_t slave_config; |
| 750 | /* Peripheral channel requires BME bit to be set when enabling the channel. */ |
| 751 | const uint32_t slave_en_mask = ESPI_SLAVE_CHANNEL_READY | |
| 752 | ESPI_SLAVE_PERIPH_BUS_MASTER_ENABLE; |
| 753 | |
| 754 | if (espi_get_configuration(ESPI_SLAVE_PERIPH_CFG, &slave_config) == -1) |
| 755 | return -1; |
| 756 | |
| 757 | /* |
| 758 | * Peripheral channel is the only one which is enabled on reset. So, if the mainboard |
| 759 | * wants to disable it, set configuration to disable peripheral channel. It also |
| 760 | * requires that BME bit be cleared. |
| 761 | */ |
| 762 | if (mb_cfg->periph_ch_en) { |
| 763 | if (!espi_slave_supports_periph_channel(slave_caps)) { |
| 764 | printk(BIOS_ERR, "Error: eSPI slave doesn't support periph channel!\n"); |
| 765 | return -1; |
| 766 | } |
| 767 | slave_config |= slave_en_mask; |
| 768 | } else { |
| 769 | slave_config &= ~slave_en_mask; |
| 770 | } |
| 771 | |
| 772 | return espi_set_channel_configuration(slave_config, ESPI_SLAVE_PERIPH_CFG, |
| 773 | ESPI_PERIPH_CH_EN); |
| 774 | } |
| 775 | |
| 776 | static int espi_setup_oob_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) |
| 777 | { |
| 778 | uint32_t slave_config; |
| 779 | |
| 780 | if (!mb_cfg->oob_ch_en) |
| 781 | return 0; |
| 782 | |
| 783 | if (!espi_slave_supports_oob_channel(slave_caps)) { |
| 784 | printk(BIOS_ERR, "Error: eSPI slave doesn't support OOB channel!\n"); |
| 785 | return -1; |
| 786 | } |
| 787 | |
| 788 | if (espi_get_configuration(ESPI_SLAVE_OOB_CFG, &slave_config) == -1) |
| 789 | return -1; |
| 790 | |
| 791 | slave_config |= ESPI_SLAVE_CHANNEL_ENABLE; |
| 792 | |
| 793 | return espi_set_channel_configuration(slave_config, ESPI_SLAVE_OOB_CFG, |
| 794 | ESPI_OOB_CH_EN); |
| 795 | } |
| 796 | |
| 797 | static int espi_setup_flash_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) |
| 798 | { |
| 799 | uint32_t slave_config; |
| 800 | |
| 801 | if (!mb_cfg->flash_ch_en) |
| 802 | return 0; |
| 803 | |
| 804 | if (!espi_slave_supports_flash_channel(slave_caps)) { |
| 805 | printk(BIOS_ERR, "Error: eSPI slave doesn't support flash channel!\n"); |
| 806 | return -1; |
| 807 | } |
| 808 | |
| 809 | if (espi_get_configuration(ESPI_SLAVE_FLASH_CFG, &slave_config) == -1) |
| 810 | return -1; |
| 811 | |
| 812 | slave_config |= ESPI_SLAVE_CHANNEL_ENABLE; |
| 813 | |
| 814 | return espi_set_channel_configuration(slave_config, ESPI_SLAVE_FLASH_CFG, |
| 815 | ESPI_FLASH_CH_EN); |
| 816 | } |
| 817 | |
| 818 | static void espi_set_initial_config(const struct espi_config *mb_cfg) |
| 819 | { |
| 820 | uint32_t espi_initial_mode = ESPI_OP_FREQ_16_MHZ | ESPI_IO_MODE_SINGLE; |
| 821 | |
| 822 | if (mb_cfg->dedicated_alert_pin) |
| 823 | espi_initial_mode |= ESPI_ALERT_MODE; |
| 824 | |
| 825 | espi_write32(ESPI_SLAVE0_CONFIG, espi_initial_mode); |
| 826 | } |
| 827 | |
| 828 | static void espi_setup_subtractive_decode(const struct espi_config *mb_cfg) |
| 829 | { |
| 830 | uint32_t global_ctrl_reg; |
| 831 | global_ctrl_reg = espi_read32(ESPI_GLOBAL_CONTROL_1); |
| 832 | |
| 833 | if (mb_cfg->subtractive_decode) { |
| 834 | global_ctrl_reg &= ~ESPI_SUB_DECODE_SLV_MASK; |
| 835 | global_ctrl_reg |= ESPI_SUB_DECODE_EN; |
| 836 | |
| 837 | } else { |
| 838 | global_ctrl_reg &= ~ESPI_SUB_DECODE_EN; |
| 839 | } |
| 840 | espi_write32(ESPI_GLOBAL_CONTROL_1, global_ctrl_reg); |
| 841 | } |
| 842 | |
| 843 | int espi_setup(void) |
| 844 | { |
| 845 | uint32_t slave_caps; |
| 846 | const struct espi_config *cfg = espi_get_config(); |
| 847 | |
| 848 | /* |
| 849 | * Boot sequence: Step 1 |
| 850 | * Set correct initial configuration to talk to the slave: |
| 851 | * Set clock frequency to 16.7MHz and single IO mode. |
| 852 | */ |
| 853 | espi_set_initial_config(cfg); |
| 854 | |
| 855 | /* |
| 856 | * Boot sequence: Step 2 |
| 857 | * Send in-band reset |
| 858 | * The resets affects both host and slave devices, so set initial config again. |
| 859 | */ |
| 860 | if (espi_send_reset() == -1) { |
| 861 | printk(BIOS_ERR, "Error: In-band reset failed!\n"); |
| 862 | return -1; |
| 863 | } |
| 864 | espi_set_initial_config(cfg); |
| 865 | |
| 866 | /* |
| 867 | * Boot sequence: Step 3 |
| 868 | * Get configuration of slave device. |
| 869 | */ |
| 870 | if (espi_get_general_configuration(&slave_caps) == -1) { |
| 871 | printk(BIOS_ERR, "Error: Slave GET_CONFIGURATION failed!\n"); |
| 872 | return -1; |
| 873 | } |
| 874 | |
| 875 | /* |
| 876 | * Boot sequence: |
| 877 | * Step 4: Write slave device general config |
| 878 | * Step 5: Set host slave config |
| 879 | */ |
| 880 | if (espi_set_general_configuration(cfg, slave_caps) == -1) { |
| 881 | printk(BIOS_ERR, "Error: Slave SET_CONFIGURATION failed!\n"); |
| 882 | return -1; |
| 883 | } |
| 884 | |
| 885 | /* |
| 886 | * Setup polarity before enabling the VW channel so any interrupts |
| 887 | * received will have the correct polarity. |
| 888 | */ |
| 889 | espi_write32(ESPI_RXVW_POLARITY, cfg->vw_irq_polarity); |
| 890 | |
| 891 | /* |
| 892 | * Boot Sequences: Steps 6 - 9 |
| 893 | * Channel setup |
| 894 | */ |
| 895 | /* Set up VW first so we can deassert PLTRST#. */ |
| 896 | if (espi_setup_vw_channel(cfg, slave_caps) == -1) { |
| 897 | printk(BIOS_ERR, "Error: Setup VW channel failed!\n"); |
| 898 | return -1; |
| 899 | } |
| 900 | |
| 901 | /* De-assert PLTRST# if VW channel is enabled by mainboard. */ |
| 902 | if (espi_send_pltrst_deassert(cfg) == -1) { |
| 903 | printk(BIOS_ERR, "Error: PLTRST deassertion failed!\n"); |
| 904 | return -1; |
| 905 | } |
| 906 | |
| 907 | if (espi_setup_periph_channel(cfg, slave_caps) == -1) { |
| 908 | printk(BIOS_ERR, "Error: Setup Periph channel failed!\n"); |
| 909 | return -1; |
| 910 | } |
| 911 | |
| 912 | if (espi_setup_oob_channel(cfg, slave_caps) == -1) { |
| 913 | printk(BIOS_ERR, "Error: Setup OOB channel failed!\n"); |
| 914 | return -1; |
| 915 | } |
| 916 | |
| 917 | if (espi_setup_flash_channel(cfg, slave_caps) == -1) { |
| 918 | printk(BIOS_ERR, "Error: Setup Flash channel failed!\n"); |
| 919 | return -1; |
| 920 | } |
| 921 | |
| 922 | /* Enable subtractive decode if configured */ |
| 923 | espi_setup_subtractive_decode(cfg); |
| 924 | |
| 925 | return 0; |
| 926 | } |