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Marc Jones24484842017-05-04 21:17:45 -06001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2017 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
Marc Jones1587dc82017-05-15 18:55:11 -060015
Marc Jones24484842017-05-04 21:17:45 -060016#include <chip.h>
Marc Jones1587dc82017-05-15 18:55:11 -060017#include <cpu/amd/mtrr.h>
18#include <cpu/cpu.h>
Marc Jones24484842017-05-04 21:17:45 -060019#include <device/device.h>
20#include <device/pci.h>
Marshall Dawsona7bfbbe2017-09-13 17:24:53 -060021#include <soc/cpu.h>
Marc Jones1587dc82017-05-15 18:55:11 -060022#include <soc/northbridge.h>
Marshall Dawsona7bfbbe2017-09-13 17:24:53 -060023#include <soc/southbridge.h>
Marc Jones24484842017-05-04 21:17:45 -060024
Marc Jones1587dc82017-05-15 18:55:11 -060025struct device_operations cpu_bus_ops = {
26 .read_resources = DEVICE_NOOP,
27 .set_resources = DEVICE_NOOP,
28 .enable_resources = DEVICE_NOOP,
Marshall Dawsona7bfbbe2017-09-13 17:24:53 -060029 .init = stoney_init_cpus,
30 .scan_bus = NULL,
Marc Jones6bfcf662017-08-06 17:42:35 -060031 .acpi_fill_ssdt_generator = generate_cpu_entries,
Marc Jones24484842017-05-04 21:17:45 -060032};
33
Marc Jones1587dc82017-05-15 18:55:11 -060034struct device_operations pci_domain_ops = {
35 .read_resources = domain_read_resources,
36 .set_resources = domain_set_resources,
37 .enable_resources = domain_enable_resources,
38 .init = NULL,
39 .scan_bus = pci_domain_scan_bus,
40 .ops_pci_bus = pci_bus_default_ops,
Marc Jones24484842017-05-04 21:17:45 -060041};
42
43static void enable_dev(device_t dev)
44{
Marc Jones1587dc82017-05-15 18:55:11 -060045 static int done = 0;
46
47 if (!done) {
48 setup_bsp_ramtop();
49 done = 1;
50 }
51
Marc Jones24484842017-05-04 21:17:45 -060052 /* Set the operations if it is a special bus type */
Marshall Dawson4e101ad2017-06-15 12:17:38 -060053 if (dev->path.type == DEVICE_PATH_DOMAIN)
Marc Jones24484842017-05-04 21:17:45 -060054 dev->ops = &pci_domain_ops;
Marshall Dawson4e101ad2017-06-15 12:17:38 -060055 else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
Marc Jones24484842017-05-04 21:17:45 -060056 dev->ops = &cpu_bus_ops;
Marshall Dawson4e101ad2017-06-15 12:17:38 -060057 else if (dev->path.type == DEVICE_PATH_PCI)
Marc Jonesdfeb1c42017-08-07 19:08:24 -060058 sb_enable(dev);
Marc Jones24484842017-05-04 21:17:45 -060059}
60
61static void soc_init(void *chip_info)
62{
Marc Jonesdfeb1c42017-08-07 19:08:24 -060063 southbridge_init(chip_info);
Marc Jones24484842017-05-04 21:17:45 -060064}
65
66static void soc_final(void *chip_info)
67{
Marc Jonesdfeb1c42017-08-07 19:08:24 -060068 southbridge_final(chip_info);
Marc Jones1587dc82017-05-15 18:55:11 -060069 fam15_finalize(chip_info);
Marc Jones24484842017-05-04 21:17:45 -060070}
71
72struct chip_operations soc_amd_stoneyridge_ops = {
73 CHIP_NAME("AMD StoneyRidge SOC")
74 .enable_dev = &enable_dev,
75 .init = &soc_init,
76 .final = &soc_final
77};