blob: 14f76b77454d950ea0c2ccc8d20e7e182ac2512d [file] [log] [blame]
Marc Jones24484842017-05-04 21:17:45 -06001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2017 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
Marc Jones1587dc82017-05-15 18:55:11 -060015
Marc Jones24484842017-05-04 21:17:45 -060016#include <chip.h>
Marc Jones1587dc82017-05-15 18:55:11 -060017#include <cpu/amd/mtrr.h>
18#include <cpu/cpu.h>
Marc Jones24484842017-05-04 21:17:45 -060019#include <device/device.h>
20#include <device/pci.h>
Marc Jonesdfeb1c42017-08-07 19:08:24 -060021#include <soc/southbridge.h>
Marc Jones1587dc82017-05-15 18:55:11 -060022#include <soc/northbridge.h>
Marc Jones24484842017-05-04 21:17:45 -060023
Marc Jones1587dc82017-05-15 18:55:11 -060024static void cpu_bus_init(device_t dev)
Marc Jones24484842017-05-04 21:17:45 -060025{
Marc Jones1587dc82017-05-15 18:55:11 -060026 initialize_cpus(dev->link_list);
Marc Jones24484842017-05-04 21:17:45 -060027}
28
Marc Jones1587dc82017-05-15 18:55:11 -060029struct device_operations cpu_bus_ops = {
30 .read_resources = DEVICE_NOOP,
31 .set_resources = DEVICE_NOOP,
32 .enable_resources = DEVICE_NOOP,
33 .init = &cpu_bus_init,
34 .scan_bus = cpu_bus_scan,
Marc Jones6bfcf662017-08-06 17:42:35 -060035 .acpi_fill_ssdt_generator = generate_cpu_entries,
Marc Jones24484842017-05-04 21:17:45 -060036};
37
Marc Jones1587dc82017-05-15 18:55:11 -060038struct device_operations pci_domain_ops = {
39 .read_resources = domain_read_resources,
40 .set_resources = domain_set_resources,
41 .enable_resources = domain_enable_resources,
42 .init = NULL,
43 .scan_bus = pci_domain_scan_bus,
44 .ops_pci_bus = pci_bus_default_ops,
Marc Jones24484842017-05-04 21:17:45 -060045};
46
47static void enable_dev(device_t dev)
48{
Marc Jones1587dc82017-05-15 18:55:11 -060049 static int done = 0;
50
51 if (!done) {
52 setup_bsp_ramtop();
53 done = 1;
54 }
55
Marc Jones24484842017-05-04 21:17:45 -060056 /* Set the operations if it is a special bus type */
Marshall Dawson4e101ad2017-06-15 12:17:38 -060057 if (dev->path.type == DEVICE_PATH_DOMAIN)
Marc Jones24484842017-05-04 21:17:45 -060058 dev->ops = &pci_domain_ops;
Marshall Dawson4e101ad2017-06-15 12:17:38 -060059 else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
Marc Jones24484842017-05-04 21:17:45 -060060 dev->ops = &cpu_bus_ops;
Marshall Dawson4e101ad2017-06-15 12:17:38 -060061 else if (dev->path.type == DEVICE_PATH_PCI)
Marc Jonesdfeb1c42017-08-07 19:08:24 -060062 sb_enable(dev);
Marc Jones24484842017-05-04 21:17:45 -060063}
64
65static void soc_init(void *chip_info)
66{
Marc Jonesdfeb1c42017-08-07 19:08:24 -060067 southbridge_init(chip_info);
Marc Jones24484842017-05-04 21:17:45 -060068}
69
70static void soc_final(void *chip_info)
71{
Marc Jonesdfeb1c42017-08-07 19:08:24 -060072 southbridge_final(chip_info);
Marc Jones1587dc82017-05-15 18:55:11 -060073 fam15_finalize(chip_info);
Marc Jones24484842017-05-04 21:17:45 -060074}
75
76struct chip_operations soc_amd_stoneyridge_ops = {
77 CHIP_NAME("AMD StoneyRidge SOC")
78 .enable_dev = &enable_dev,
79 .init = &soc_init,
80 .final = &soc_final
81};