blob: 2af466bc8f25cf93c91eda83e2598fb6bb5535bf [file] [log] [blame]
Marc Jones24484842017-05-04 21:17:45 -06001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2017 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
Marc Jones1587dc82017-05-15 18:55:11 -060015
Marc Jones24484842017-05-04 21:17:45 -060016#include <chip.h>
Marc Jones1587dc82017-05-15 18:55:11 -060017#include <cpu/amd/mtrr.h>
18#include <cpu/cpu.h>
Marc Jones24484842017-05-04 21:17:45 -060019#include <device/device.h>
20#include <device/pci.h>
21#include <soc/hudson.h>
Marc Jones1587dc82017-05-15 18:55:11 -060022#include <soc/northbridge.h>
Marc Jones24484842017-05-04 21:17:45 -060023
Marc Jones1587dc82017-05-15 18:55:11 -060024static void cpu_bus_init(device_t dev)
Marc Jones24484842017-05-04 21:17:45 -060025{
Marc Jones1587dc82017-05-15 18:55:11 -060026 initialize_cpus(dev->link_list);
Marc Jones24484842017-05-04 21:17:45 -060027}
28
Marc Jones1587dc82017-05-15 18:55:11 -060029struct device_operations cpu_bus_ops = {
30 .read_resources = DEVICE_NOOP,
31 .set_resources = DEVICE_NOOP,
32 .enable_resources = DEVICE_NOOP,
33 .init = &cpu_bus_init,
34 .scan_bus = cpu_bus_scan,
Marc Jones24484842017-05-04 21:17:45 -060035};
36
Marc Jones1587dc82017-05-15 18:55:11 -060037struct device_operations pci_domain_ops = {
38 .read_resources = domain_read_resources,
39 .set_resources = domain_set_resources,
40 .enable_resources = domain_enable_resources,
41 .init = NULL,
42 .scan_bus = pci_domain_scan_bus,
43 .ops_pci_bus = pci_bus_default_ops,
Marc Jones24484842017-05-04 21:17:45 -060044};
45
46static void enable_dev(device_t dev)
47{
Marc Jones1587dc82017-05-15 18:55:11 -060048 static int done = 0;
49
50 if (!done) {
51 setup_bsp_ramtop();
52 done = 1;
53 }
54
Marc Jones24484842017-05-04 21:17:45 -060055 /* Set the operations if it is a special bus type */
Marshall Dawson4e101ad2017-06-15 12:17:38 -060056 if (dev->path.type == DEVICE_PATH_DOMAIN)
Marc Jones24484842017-05-04 21:17:45 -060057 dev->ops = &pci_domain_ops;
Marshall Dawson4e101ad2017-06-15 12:17:38 -060058 else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
Marc Jones24484842017-05-04 21:17:45 -060059 dev->ops = &cpu_bus_ops;
Marshall Dawson4e101ad2017-06-15 12:17:38 -060060 else if (dev->path.type == DEVICE_PATH_PCI)
Marc Jones24484842017-05-04 21:17:45 -060061 hudson_enable(dev);
Marc Jones24484842017-05-04 21:17:45 -060062}
63
64static void soc_init(void *chip_info)
65{
66 hudson_init(chip_info);
67}
68
69static void soc_final(void *chip_info)
70{
71 hudson_final(chip_info);
Marc Jones1587dc82017-05-15 18:55:11 -060072 fam15_finalize(chip_info);
Marc Jones24484842017-05-04 21:17:45 -060073}
74
75struct chip_operations soc_amd_stoneyridge_ops = {
76 CHIP_NAME("AMD StoneyRidge SOC")
77 .enable_dev = &enable_dev,
78 .init = &soc_init,
79 .final = &soc_final
80};