Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2017 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 15 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 16 | #include <chip.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 17 | #include <cpu/amd/mtrr.h> |
| 18 | #include <cpu/cpu.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 19 | #include <device/device.h> |
| 20 | #include <device/pci.h> |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame^] | 21 | #include <soc/southbridge.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 22 | #include <soc/northbridge.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 23 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 24 | static void cpu_bus_init(device_t dev) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 25 | { |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 26 | initialize_cpus(dev->link_list); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 27 | } |
| 28 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 29 | struct device_operations cpu_bus_ops = { |
| 30 | .read_resources = DEVICE_NOOP, |
| 31 | .set_resources = DEVICE_NOOP, |
| 32 | .enable_resources = DEVICE_NOOP, |
| 33 | .init = &cpu_bus_init, |
| 34 | .scan_bus = cpu_bus_scan, |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 35 | }; |
| 36 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 37 | struct device_operations pci_domain_ops = { |
| 38 | .read_resources = domain_read_resources, |
| 39 | .set_resources = domain_set_resources, |
| 40 | .enable_resources = domain_enable_resources, |
| 41 | .init = NULL, |
| 42 | .scan_bus = pci_domain_scan_bus, |
| 43 | .ops_pci_bus = pci_bus_default_ops, |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 44 | }; |
| 45 | |
| 46 | static void enable_dev(device_t dev) |
| 47 | { |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 48 | static int done = 0; |
| 49 | |
| 50 | if (!done) { |
| 51 | setup_bsp_ramtop(); |
| 52 | done = 1; |
| 53 | } |
| 54 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 55 | /* Set the operations if it is a special bus type */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 56 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 57 | dev->ops = &pci_domain_ops; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 58 | else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 59 | dev->ops = &cpu_bus_ops; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 60 | else if (dev->path.type == DEVICE_PATH_PCI) |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame^] | 61 | sb_enable(dev); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 62 | } |
| 63 | |
| 64 | static void soc_init(void *chip_info) |
| 65 | { |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame^] | 66 | southbridge_init(chip_info); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 67 | } |
| 68 | |
| 69 | static void soc_final(void *chip_info) |
| 70 | { |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame^] | 71 | southbridge_final(chip_info); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 72 | fam15_finalize(chip_info); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 73 | } |
| 74 | |
| 75 | struct chip_operations soc_amd_stoneyridge_ops = { |
| 76 | CHIP_NAME("AMD StoneyRidge SOC") |
| 77 | .enable_dev = &enable_dev, |
| 78 | .init = &soc_init, |
| 79 | .final = &soc_final |
| 80 | }; |