Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 1 | config SOC_INTEL_APOLLOLAKE |
| 2 | bool |
Arthur Heymans | 5e8c906 | 2021-06-15 11:19:52 +0200 | [diff] [blame] | 3 | select INTEL_CAR_CQOS |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 4 | help |
| 5 | Intel Apollolake support |
| 6 | |
Angel Pons | b36100f | 2020-09-07 13:18:10 +0200 | [diff] [blame] | 7 | config SOC_INTEL_GEMINILAKE |
Hannah Williams | 3ff14a0 | 2017-05-05 16:30:22 -0700 | [diff] [blame] | 8 | bool |
| 9 | default n |
| 10 | select SOC_INTEL_APOLLOLAKE |
Furquan Shaikh | 23e8813 | 2020-10-08 23:44:20 -0700 | [diff] [blame] | 11 | select SOC_INTEL_COMMON_BLOCK_CNVI |
Pratik Prajapati | dc194e2 | 2017-08-29 14:27:07 -0700 | [diff] [blame] | 12 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
| 13 | select SOC_INTEL_COMMON_BLOCK_SGX |
Ravi Sarawadi | 3669a06 | 2018-02-27 13:23:42 -0800 | [diff] [blame] | 14 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
Aaron Durbin | 82d0f91 | 2018-04-21 00:16:28 -0600 | [diff] [blame] | 15 | select IDT_IN_EVERY_STAGE |
Aaron Durbin | 5c9df70 | 2018-04-18 01:05:25 -0600 | [diff] [blame] | 16 | select PAGING_IN_CACHE_AS_RAM |
Arthur Heymans | 5e8c906 | 2021-06-15 11:19:52 +0200 | [diff] [blame] | 17 | select INTEL_CAR_NEM |
Hannah Williams | 3ff14a0 | 2017-05-05 16:30:22 -0700 | [diff] [blame] | 18 | help |
| 19 | Intel GLK support |
| 20 | |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 21 | if SOC_INTEL_APOLLOLAKE |
| 22 | |
| 23 | config CPU_SPECIFIC_OPTIONS |
| 24 | def_bool y |
Aaron Durbin | ed35b7c | 2016-07-13 23:17:38 -0500 | [diff] [blame] | 25 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Nico Huber | 44c6cf6 | 2018-11-24 17:53:17 +0100 | [diff] [blame] | 26 | select ACPI_NO_PCAT_8259 |
Angel Pons | 8e035e3 | 2021-06-22 12:58:20 +0200 | [diff] [blame] | 27 | select ARCH_X86 |
Aaron Durbin | e8e118d | 2016-08-12 15:00:10 -0500 | [diff] [blame] | 28 | select BOOT_DEVICE_SUPPORTS_WRITES |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 29 | # CPU specific options |
Angel Pons | ae0d8d6 | 2020-09-02 15:00:40 +0200 | [diff] [blame] | 30 | select CPU_INTEL_COMMON |
Michael Niewöhner | fe6070f | 2020-10-04 15:16:04 +0200 | [diff] [blame] | 31 | select CPU_SUPPORTS_PM_TIMER_EMULATION |
Subrata Banik | ccd8700 | 2017-03-08 17:55:26 +0530 | [diff] [blame] | 32 | select PCR_COMMON_IOSF_1_0 |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 33 | select SSE2 |
| 34 | select SUPPORT_CPU_UCODE_IN_CBFS |
Saurabh Satija | 734aa87 | 2016-06-21 14:22:16 -0700 | [diff] [blame] | 35 | # Audio options |
| 36 | select ACPI_NHLT |
| 37 | select SOC_INTEL_COMMON_NHLT |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 38 | # Misc options |
Aaron Durbin | 934f433 | 2017-12-15 12:59:18 -0700 | [diff] [blame] | 39 | select CACHE_MRC_SETTINGS |
Sean Rhodes | 7bbc9a5 | 2022-07-18 11:31:00 +0100 | [diff] [blame] | 40 | select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 |
Werner Zeh | b60e69b | 2022-05-17 10:19:19 +0200 | [diff] [blame] | 41 | select FAST_SPI_GENERATE_SSDT |
Ravi Sarawadi | a3d13fbd6 | 2017-04-25 19:30:58 -0700 | [diff] [blame] | 42 | select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 43 | select FSP_STATUS_GLOBAL_RESET_REQUIRED_5 |
Duncan Laurie | d25dd99 | 2016-06-29 10:47:48 -0700 | [diff] [blame] | 44 | select GENERIC_GPIO_LIB |
Subrata Banik | 34f26b2 | 2022-02-10 12:38:02 +0530 | [diff] [blame] | 45 | select HAVE_ASAN_IN_ROMSTAGE |
| 46 | select HAVE_CF9_RESET_PREPARE |
Subrata Banik | 4225a79 | 2022-12-19 18:24:13 +0530 | [diff] [blame] | 47 | select HAVE_DPTF_EISA_HID |
Subrata Banik | 34f26b2 | 2022-02-10 12:38:02 +0530 | [diff] [blame] | 48 | select HAVE_FSP_GOP |
| 49 | select HAVE_FSP_LOGO_SUPPORT |
Angel Pons | b36100f | 2020-09-07 13:18:10 +0200 | [diff] [blame] | 50 | select HAVE_INTEL_FSP_REPO if !SOC_INTEL_GEMINILAKE |
Subrata Banik | 34f26b2 | 2022-02-10 12:38:02 +0530 | [diff] [blame] | 51 | select HAVE_SMI_HANDLER |
| 52 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
| 53 | select INTEL_GMA_ACPI |
| 54 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
| 55 | select INTEL_GMA_SWSMISCI |
Furquan Shaikh | ffb3a2d | 2016-10-24 15:28:23 -0700 | [diff] [blame] | 56 | select MRC_SETTINGS_PROTECT |
Aaron Durbin | 934f433 | 2017-12-15 12:59:18 -0700 | [diff] [blame] | 57 | select MRC_SETTINGS_VARIABLE_DATA |
Michael Niewöhner | c9a12f2 | 2021-09-24 23:22:51 +0200 | [diff] [blame] | 58 | select NO_PM_ACPI_TIMER |
Subrata Banik | 34f26b2 | 2022-02-10 12:38:02 +0530 | [diff] [blame] | 59 | select NO_UART_ON_SUPERIO |
| 60 | select NO_XIP_EARLY_STAGES |
Arthur Heymans | e247435 | 2020-11-30 15:42:49 +0100 | [diff] [blame] | 61 | select FSP_COMPRESS_FSP_M_LZ4 |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame] | 62 | select PARALLEL_MP_AP_WORK |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 63 | select PCIEXP_ASPM |
| 64 | select PCIEXP_COMMON_CLOCK |
| 65 | select PCIEXP_CLK_PM |
| 66 | select PCIEXP_L1_SUB_STATE |
Michał Żygowski | c68456e | 2023-01-18 13:37:28 +0100 | [diff] [blame] | 67 | select PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B |
Subrata Banik | 34f26b2 | 2022-02-10 12:38:02 +0530 | [diff] [blame] | 68 | select PLATFORM_USES_FSP2_0 |
Hannah Williams | 1177bf5 | 2017-12-13 12:44:26 -0800 | [diff] [blame] | 69 | select PMC_INVALID_READ_AFTER_WRITE |
Julien Viard de Galbert | 2912e8e | 2018-08-14 16:15:26 +0200 | [diff] [blame] | 70 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 71 | select REG_SCRIPT |
Subrata Banik | 208587e | 2017-05-19 18:38:24 +0530 | [diff] [blame] | 72 | select SA_ENABLE_IMR |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 73 | select SOC_INTEL_COMMON |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame] | 74 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
Subrata Banik | fc4c7d8 | 2017-03-03 18:23:59 +0530 | [diff] [blame] | 75 | select SOC_INTEL_COMMON_BLOCK |
Sumeet R Pawnikar | 2adb50d | 2020-05-09 15:37:09 +0530 | [diff] [blame] | 76 | select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 77 | select SOC_INTEL_COMMON_BLOCK_ACPI |
Arthur Heymans | 5e8c906 | 2021-06-15 11:19:52 +0200 | [diff] [blame] | 78 | select SOC_INTEL_COMMON_BLOCK_CAR |
Barnali Sarkar | 66fe0c4 | 2017-05-23 18:17:14 +0530 | [diff] [blame] | 79 | select SOC_INTEL_COMMON_BLOCK_CPU |
Furquan Shaikh | 2c36889 | 2018-10-18 16:22:37 -0700 | [diff] [blame] | 80 | select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT |
Aaron Durbin | aa2504a | 2017-07-14 16:53:49 -0600 | [diff] [blame] | 81 | select SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES |
Hannah Williams | 12bed18 | 2017-05-26 20:31:15 -0700 | [diff] [blame] | 82 | select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY |
Subrata Banik | c176fc2 | 2022-04-25 16:59:35 +0530 | [diff] [blame] | 83 | select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR |
Sean Rhodes | 026f0047 | 2022-06-20 08:09:29 +0100 | [diff] [blame] | 84 | select SOC_INTEL_COMMON_PCH_CLIENT |
Arthur Heymans | 1ae8cd1 | 2020-11-19 13:59:53 +0100 | [diff] [blame] | 85 | select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE |
V Sowmya | 45a2138 | 2017-11-27 12:39:10 +0530 | [diff] [blame] | 86 | select SOC_INTEL_COMMON_BLOCK_SRAM |
Aamir Bohra | bf6dfae | 2017-04-07 21:10:27 +0530 | [diff] [blame] | 87 | select SOC_INTEL_COMMON_BLOCK_SA |
Bora Guvendik | 65623b7 | 2017-05-08 16:29:17 -0700 | [diff] [blame] | 88 | select SOC_INTEL_COMMON_BLOCK_SCS |
Karthikeyan Ramasubramanian | f84c103 | 2019-03-20 13:15:00 -0600 | [diff] [blame] | 89 | select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG |
Brandon Breitenstein | a86d1b8 | 2017-06-08 17:32:02 -0700 | [diff] [blame] | 90 | select SOC_INTEL_COMMON_BLOCK_SMM |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 91 | select SOC_INTEL_COMMON_FSP_RESET |
Subrata Banik | 34f26b2 | 2022-02-10 12:38:02 +0530 | [diff] [blame] | 92 | select SOC_INTEL_COMMON_RESET |
Sean Rhodes | 026f0047 | 2022-06-20 08:09:29 +0100 | [diff] [blame] | 93 | select SOC_INTEL_INTEGRATED_SOUTHCLUSTER |
Subrata Banik | af27ac2 | 2022-02-18 00:44:15 +0530 | [diff] [blame] | 94 | select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION |
Arthur Heymans | 6da7fa2 | 2021-06-23 10:52:01 +0200 | [diff] [blame] | 95 | select SOC_INTEL_NO_BOOTGUARD_MSR |
Hannah Williams | b13d454 | 2016-03-14 17:38:51 -0700 | [diff] [blame] | 96 | select TSC_MONOTONIC_TIMER |
Subrata Banik | 34f26b2 | 2022-02-10 12:38:02 +0530 | [diff] [blame] | 97 | select UDELAY_TSC |
Patrick Rudolph | 05ca054 | 2022-03-22 08:33:40 +0100 | [diff] [blame] | 98 | select UDK_2017_BINDING |
Subrata Banik | 34f26b2 | 2022-02-10 12:38:02 +0530 | [diff] [blame] | 99 | select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM |
| 100 | select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT |
| 101 | select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE |
Raul E Rangel | e92a982 | 2021-06-24 16:54:27 -0600 | [diff] [blame] | 102 | # This SoC does not map SPI flash like many previous SoC. Therefore we |
| 103 | # provide a custom media driver that facilitates mapping |
| 104 | select X86_CUSTOM_BOOTMEDIA |
Zhao, Lijian | d8d42c2 | 2016-03-14 14:19:22 -0700 | [diff] [blame] | 105 | |
Sean Rhodes | fafcb74 | 2022-01-20 21:28:31 +0000 | [diff] [blame] | 106 | config SKIP_CSE_RBP |
| 107 | bool |
| 108 | default y if BOOT_DEVICE_MEMORY_MAPPED |
| 109 | help |
| 110 | Tell CSE we do not need to use Ring Buffer Protocol (RBP) to fetch |
| 111 | firmware for us if we are using memory-mapped SPI. This lets CSE |
| 112 | state machine transition to next boot state, so that it can function |
| 113 | as designed. |
| 114 | |
Subrata Banik | 206b0bc | 2022-01-06 09:34:43 +0000 | [diff] [blame] | 115 | config DISABLE_HECI1_AT_PRE_BOOT |
| 116 | default y |
| 117 | |
Subrata Banik | 526cc3e | 2022-01-31 21:55:51 +0530 | [diff] [blame] | 118 | config MAX_HECI_DEVICES |
| 119 | int |
Sean Rhodes | 843f34e | 2022-06-01 11:30:31 +0100 | [diff] [blame] | 120 | default 3 |
Subrata Banik | 526cc3e | 2022-01-31 21:55:51 +0530 | [diff] [blame] | 121 | |
Angel Pons | f4779e8 | 2020-09-07 13:40:47 +0200 | [diff] [blame] | 122 | config MAX_CPUS |
| 123 | int |
Angel Pons | c6c9b9c | 2020-09-07 13:45:53 +0200 | [diff] [blame] | 124 | default 4 |
Angel Pons | f4779e8 | 2020-09-07 13:40:47 +0200 | [diff] [blame] | 125 | |
Julius Werner | 58c3938 | 2017-02-13 17:53:29 -0800 | [diff] [blame] | 126 | config VBOOT |
| 127 | select VBOOT_SEPARATE_VERSTAGE |
Joel Kitching | 6672bd8 | 2019-04-10 16:06:21 +0800 | [diff] [blame] | 128 | select VBOOT_MUST_REQUEST_DISPLAY |
Furquan Shaikh | 87b1bcc | 2016-07-22 12:57:51 -0700 | [diff] [blame] | 129 | select VBOOT_STARTS_IN_BOOTBLOCK |
Sean Rhodes | d86860b | 2022-07-18 10:45:06 +0100 | [diff] [blame] | 130 | select VBOOT_VBNV_CMOS if !VBOOT_VBNV_FLASH |
| 131 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH if !VBOOT_VBNV_FLASH |
Furquan Shaikh | 87b1bcc | 2016-07-22 12:57:51 -0700 | [diff] [blame] | 132 | |
Aaron Durbin | 80a3df2 | 2016-04-27 23:05:52 -0500 | [diff] [blame] | 133 | config TPM_ON_FAST_SPI |
| 134 | bool |
| 135 | default n |
Jes B. Klinke | c6b041a1 | 2022-04-19 14:00:33 -0700 | [diff] [blame] | 136 | depends on MEMORY_MAPPED_TPM |
Aaron Durbin | 80a3df2 | 2016-04-27 23:05:52 -0500 | [diff] [blame] | 137 | help |
Jes B. Klinke | c6b041a1 | 2022-04-19 14:00:33 -0700 | [diff] [blame] | 138 | TPM part is conntected on Fast SPI interface and is mapped to the |
| 139 | linear address space. |
Aaron Durbin | 80a3df2 | 2016-04-27 23:05:52 -0500 | [diff] [blame] | 140 | |
Subrata Banik | ccd8700 | 2017-03-08 17:55:26 +0530 | [diff] [blame] | 141 | config PCR_BASE_ADDRESS |
| 142 | hex |
Alexandru Gagniuc | dfc2b31 | 2015-10-06 17:16:41 -0700 | [diff] [blame] | 143 | default 0xd0000000 |
Subrata Banik | ccd8700 | 2017-03-08 17:55:26 +0530 | [diff] [blame] | 144 | help |
| 145 | This option allows you to select MMIO Base Address of sideband bus. |
Alexandru Gagniuc | dfc2b31 | 2015-10-06 17:16:41 -0700 | [diff] [blame] | 146 | |
| 147 | config DCACHE_RAM_BASE |
Arthur Heymans | 3038b48 | 2017-06-13 14:05:09 +0200 | [diff] [blame] | 148 | hex |
Alexandru Gagniuc | dfc2b31 | 2015-10-06 17:16:41 -0700 | [diff] [blame] | 149 | default 0xfef00000 |
| 150 | |
| 151 | config DCACHE_RAM_SIZE |
Arthur Heymans | 3038b48 | 2017-06-13 14:05:09 +0200 | [diff] [blame] | 152 | hex |
Angel Pons | b36100f | 2020-09-07 13:18:10 +0200 | [diff] [blame] | 153 | default 0x100000 if SOC_INTEL_GEMINILAKE |
Andrey Petrov | 0dde291 | 2016-06-27 15:21:26 -0700 | [diff] [blame] | 154 | default 0xc0000 |
Alexandru Gagniuc | dfc2b31 | 2015-10-06 17:16:41 -0700 | [diff] [blame] | 155 | help |
| 156 | The size of the cache-as-ram region required during bootblock |
| 157 | and/or romstage. |
| 158 | |
| 159 | config DCACHE_BSP_STACK_SIZE |
| 160 | hex |
| 161 | default 0x4000 |
| 162 | help |
| 163 | The amount of anticipated stack usage in CAR by bootblock and |
| 164 | other stages. |
| 165 | |
Aaron Durbin | 551e4be | 2018-04-10 09:24:54 -0600 | [diff] [blame] | 166 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
Duncan Laurie | ff8bce0 | 2016-06-27 10:57:13 -0700 | [diff] [blame] | 167 | int |
Aaron Durbin | 24de597 | 2018-04-10 09:28:42 -0600 | [diff] [blame] | 168 | default 100 |
Duncan Laurie | ff8bce0 | 2016-06-27 10:57:13 -0700 | [diff] [blame] | 169 | |
Michael Niewöhner | dadcbfb | 2020-10-04 14:48:05 +0200 | [diff] [blame] | 170 | config CPU_XTAL_HZ |
| 171 | default 19200000 |
| 172 | |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 173 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 174 | int |
Aaron Durbin | 24de597 | 2018-04-10 09:28:42 -0600 | [diff] [blame] | 175 | default 133 |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 176 | |
Aaron Durbin | ada13ed | 2016-02-11 14:47:33 -0600 | [diff] [blame] | 177 | # 32KiB bootblock is all that is mapped in by the CSE at top of 4GiB. |
| 178 | config C_ENV_BOOTBLOCK_SIZE |
| 179 | hex |
| 180 | default 0x8000 |
| 181 | |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 182 | config ROMSTAGE_ADDR |
| 183 | hex |
Andrey Petrov | 7f72c9b | 2016-06-24 18:15:09 -0700 | [diff] [blame] | 184 | default 0xfef20000 |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 185 | help |
| 186 | The base address (in CAR) where romstage should be linked |
| 187 | |
Aaron Durbin | bef75e7 | 2016-05-26 11:00:44 -0500 | [diff] [blame] | 188 | config VERSTAGE_ADDR |
| 189 | hex |
Andrey Petrov | 7f72c9b | 2016-06-24 18:15:09 -0700 | [diff] [blame] | 190 | default 0xfef40000 |
Aaron Durbin | bef75e7 | 2016-05-26 11:00:44 -0500 | [diff] [blame] | 191 | help |
| 192 | The base address (in CAR) where verstage should be linked |
| 193 | |
Patrick Georgi | 6539e10 | 2018-09-13 11:48:43 -0400 | [diff] [blame] | 194 | config FSP_HEADER_PATH |
Sean Rhodes | 412222a | 2022-05-19 22:02:48 +0100 | [diff] [blame] | 195 | default "src/vendorcode/intel/fsp/fsp2_0/glk/2.2.0.0" if VENDOR_GOOGLE && SOC_INTEL_GEMINILAKE |
| 196 | default "src/vendorcode/intel/fsp/fsp2_0/glk/2.2.3.1" if SOC_INTEL_GEMINILAKE |
Patrick Georgi | 6539e10 | 2018-09-13 11:48:43 -0400 | [diff] [blame] | 197 | default "3rdparty/fsp/ApolloLakeFspBinPkg/Include/" |
| 198 | |
| 199 | config FSP_FD_PATH |
Patrick Georgi | 6539e10 | 2018-09-13 11:48:43 -0400 | [diff] [blame] | 200 | default "3rdparty/fsp/ApolloLakeFspBinPkg/FspBin/Fsp.fd" |
| 201 | |
Andrey Petrov | 79091db7 | 2016-05-17 00:03:27 -0700 | [diff] [blame] | 202 | config FSP_M_ADDR |
| 203 | hex |
Andrey Petrov | 7f72c9b | 2016-06-24 18:15:09 -0700 | [diff] [blame] | 204 | default 0xfef40000 |
Andrey Petrov | 79091db7 | 2016-05-17 00:03:27 -0700 | [diff] [blame] | 205 | help |
| 206 | The address FSP-M will be relocated to during build time |
| 207 | |
Aaron Durbin | 9f444c3 | 2016-05-20 10:48:44 -0500 | [diff] [blame] | 208 | config NEED_LBP2 |
| 209 | bool "Write contents for logical boot partition 2." |
| 210 | default n |
| 211 | help |
| 212 | Write the contents from a file into the logical boot partition 2 |
| 213 | region defined by LBP2_FMAP_NAME. |
| 214 | |
| 215 | config LBP2_FMAP_NAME |
| 216 | string "Name of FMAP region to put logical boot partition 2" |
| 217 | depends on NEED_LBP2 |
| 218 | default "SIGN_CSE" |
| 219 | help |
| 220 | Name of FMAP region to write logical boot partition 2 data. |
| 221 | |
Jeremy Compostella | 0f9858f | 2019-12-12 14:39:11 -0700 | [diff] [blame] | 222 | config LBP2_FROM_IFWI |
| 223 | bool "Extract the LBP2 from the IFWI binary" |
| 224 | depends on NEED_LBP2 |
| 225 | default n |
| 226 | help |
| 227 | The Logical Boot Partition will be automatically extracted |
| 228 | from the supplied IFWI binary |
| 229 | |
Aaron Durbin | 9f444c3 | 2016-05-20 10:48:44 -0500 | [diff] [blame] | 230 | config LBP2_FILE_NAME |
| 231 | string "Path of file to write to logical boot partition 2 region" |
Jeremy Compostella | 0f9858f | 2019-12-12 14:39:11 -0700 | [diff] [blame] | 232 | depends on NEED_LBP2 && !LBP2_FROM_IFWI |
Patrick Georgi | b8fba86 | 2020-06-17 21:06:53 +0200 | [diff] [blame] | 233 | default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/lbp2.bin" |
Aaron Durbin | 9f444c3 | 2016-05-20 10:48:44 -0500 | [diff] [blame] | 234 | help |
| 235 | Name of file to store in the logical boot partition 2 region. |
| 236 | |
Furquan Shaikh | 7043bf3 | 2016-05-28 12:57:05 -0700 | [diff] [blame] | 237 | config NEED_IFWI |
| 238 | bool "Write content into IFWI region" |
| 239 | default n |
| 240 | help |
| 241 | Write the content from a file into IFWI region defined by |
| 242 | IFWI_FMAP_NAME. |
| 243 | |
| 244 | config IFWI_FMAP_NAME |
| 245 | string "Name of FMAP region to pull IFWI into" |
| 246 | depends on NEED_IFWI |
| 247 | default "IFWI" |
| 248 | help |
| 249 | Name of FMAP region to write IFWI. |
| 250 | |
| 251 | config IFWI_FILE_NAME |
| 252 | string "Path of file to write to IFWI region" |
| 253 | depends on NEED_IFWI |
Patrick Georgi | b8fba86 | 2020-06-17 21:06:53 +0200 | [diff] [blame] | 254 | default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/ifwi.bin" |
Furquan Shaikh | 7043bf3 | 2016-05-28 12:57:05 -0700 | [diff] [blame] | 255 | help |
| 256 | Name of file to store in the IFWI region. |
| 257 | |
Sathyanarayana Nujella | c446704 | 2016-10-26 17:38:49 -0700 | [diff] [blame] | 258 | config HEAP_SIZE |
| 259 | hex |
| 260 | default 0x8000 |
| 261 | |
Sean Rhodes | 026f0047 | 2022-06-20 08:09:29 +0100 | [diff] [blame] | 262 | config MAX_ROOT_PORTS |
| 263 | int |
| 264 | default 6 |
| 265 | |
Sathyanarayana Nujella | 3e0a3fb | 2016-10-26 17:31:36 -0700 | [diff] [blame] | 266 | config NHLT_DMIC_1CH_16B |
| 267 | bool |
| 268 | depends on ACPI_NHLT |
| 269 | default n |
| 270 | help |
| 271 | Include DSP firmware settings for 1 channel 16B DMIC array. |
| 272 | |
Saurabh Satija | 734aa87 | 2016-06-21 14:22:16 -0700 | [diff] [blame] | 273 | config NHLT_DMIC_2CH_16B |
| 274 | bool |
| 275 | depends on ACPI_NHLT |
| 276 | default n |
| 277 | help |
| 278 | Include DSP firmware settings for 2 channel 16B DMIC array. |
| 279 | |
Sathyanarayana Nujella | 3e0a3fb | 2016-10-26 17:31:36 -0700 | [diff] [blame] | 280 | config NHLT_DMIC_4CH_16B |
| 281 | bool |
| 282 | depends on ACPI_NHLT |
| 283 | default n |
| 284 | help |
| 285 | Include DSP firmware settings for 4 channel 16B DMIC array. |
| 286 | |
Saurabh Satija | 734aa87 | 2016-06-21 14:22:16 -0700 | [diff] [blame] | 287 | config NHLT_MAX98357 |
| 288 | bool |
| 289 | depends on ACPI_NHLT |
| 290 | default n |
| 291 | help |
| 292 | Include DSP firmware settings for headset codec. |
| 293 | |
| 294 | config NHLT_DA7219 |
| 295 | bool |
| 296 | depends on ACPI_NHLT |
| 297 | default n |
| 298 | help |
| 299 | Include DSP firmware settings for headset codec. |
Subrata Banik | fc4c7d8 | 2017-03-03 18:23:59 +0530 | [diff] [blame] | 300 | |
Naveen Manohar | 532b8d5 | 2018-04-27 15:24:45 +0530 | [diff] [blame] | 301 | config NHLT_RT5682 |
| 302 | bool |
| 303 | depends on ACPI_NHLT |
| 304 | default n |
| 305 | help |
| 306 | Include DSP firmware settings for headset codec. |
Subrata Banik | 8e1c12f1 | 2017-03-10 13:51:11 +0530 | [diff] [blame] | 307 | # |
| 308 | # Each bit in QOS mask controls this many bytes. This is calculated as: |
| 309 | # (CACHE_WAYS / CACHE_BITS_PER_MASK) * CACHE_LINE_SIZE * CACHE_SETS |
| 310 | # |
| 311 | |
| 312 | config CACHE_QOS_SIZE_PER_BIT |
| 313 | hex |
| 314 | default 0x20000 # 128 KB |
| 315 | |
| 316 | config L2_CACHE_SIZE |
| 317 | hex |
Angel Pons | b36100f | 2020-09-07 13:18:10 +0200 | [diff] [blame] | 318 | default 0x400000 if SOC_INTEL_GEMINILAKE |
Subrata Banik | 8e1c12f1 | 2017-03-10 13:51:11 +0530 | [diff] [blame] | 319 | default 0x100000 |
| 320 | |
Brandon Breitenstein | 135eae9 | 2016-09-30 13:57:12 -0700 | [diff] [blame] | 321 | config SMM_RESERVED_SIZE |
| 322 | hex |
| 323 | default 0x100000 |
| 324 | |
Sean Rhodes | dd582b0 | 2022-06-27 08:47:10 +0100 | [diff] [blame] | 325 | config CHIPSET_DEVICETREE |
| 326 | string |
| 327 | default "soc/intel/apollolake/chipset_glk.cb" if SOC_INTEL_GEMINILAKE |
| 328 | default "soc/intel/apollolake/chipset_apl.cb" |
| 329 | |
Andrey Petrov | 4c5b31e | 2016-11-06 23:43:57 -0800 | [diff] [blame] | 330 | config IFD_CHIPSET |
| 331 | string |
Angel Pons | b36100f | 2020-09-07 13:18:10 +0200 | [diff] [blame] | 332 | default "glk" if SOC_INTEL_GEMINILAKE |
Andrey Petrov | 4c5b31e | 2016-11-06 23:43:57 -0800 | [diff] [blame] | 333 | default "aplk" |
| 334 | |
Aamir Bohra | 22b2c79 | 2017-06-02 19:07:56 +0530 | [diff] [blame] | 335 | config CPU_BCLK_MHZ |
| 336 | int |
| 337 | default 100 |
| 338 | |
Nico Huber | 9995418 | 2019-05-29 23:33:06 +0200 | [diff] [blame] | 339 | config CONSOLE_UART_BASE_ADDRESS |
| 340 | hex |
| 341 | default 0xddffc000 |
| 342 | depends on INTEL_LPSS_UART_FOR_CONSOLE |
| 343 | |
Furquan Shaikh | 3406dd6 | 2017-08-04 15:58:26 -0700 | [diff] [blame] | 344 | # M and N divisor values for clock frequency configuration. |
| 345 | # These values get us a 1.836 MHz clock (ideally we want 1.843 MHz) |
| 346 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 347 | hex |
| 348 | default 0x25a |
| 349 | |
| 350 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 351 | hex |
| 352 | default 0x7fff |
| 353 | |
Bora Guvendik | 94aed8d | 2017-11-03 12:40:25 -0700 | [diff] [blame] | 354 | config SOC_ESPI |
| 355 | bool |
| 356 | default n |
| 357 | help |
| 358 | Use eSPI bus instead of LPC |
| 359 | |
Ravi Sarawadi | 3669a06 | 2018-02-27 13:23:42 -0800 | [diff] [blame] | 360 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 361 | int |
| 362 | default 3 |
| 363 | |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 364 | config SOC_INTEL_I2C_DEV_MAX |
| 365 | int |
| 366 | default 8 |
| 367 | |
Aaron Durbin | 5c9df70 | 2018-04-18 01:05:25 -0600 | [diff] [blame] | 368 | # Don't include the early page tables in RW_A or RW_B cbfs regions |
| 369 | config RO_REGION_ONLY |
| 370 | string |
| 371 | default "pdpt pt" |
| 372 | |
Matt DeVillier | d7ef450 | 2020-04-21 01:23:10 -0500 | [diff] [blame] | 373 | config INTEL_GMA_PANEL_2 |
| 374 | bool |
| 375 | default n |
| 376 | |
| 377 | config INTEL_GMA_BCLV_OFFSET |
| 378 | default 0xc8358 if INTEL_GMA_PANEL_2 |
| 379 | default 0xc8258 |
| 380 | |
| 381 | config INTEL_GMA_BCLV_WIDTH |
| 382 | default 32 |
| 383 | |
| 384 | config INTEL_GMA_BCLM_OFFSET |
| 385 | default 0xc8354 if INTEL_GMA_PANEL_2 |
| 386 | default 0xc8254 |
| 387 | |
| 388 | config INTEL_GMA_BCLM_WIDTH |
| 389 | default 32 |
| 390 | |
Arthur Heymans | 7e0af33 | 2022-03-30 23:04:35 +0200 | [diff] [blame] | 391 | config BOOTBLOCK_IN_CBFS |
| 392 | bool |
| 393 | default n |
| 394 | |
Sean Rhodes | 026f0047 | 2022-06-20 08:09:29 +0100 | [diff] [blame] | 395 | config HAVE_PAM0_REGISTER |
| 396 | bool |
| 397 | default n |
| 398 | |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 399 | endif |