Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 1 | config SOC_INTEL_TIGERLAKE |
| 2 | bool |
| 3 | help |
| 4 | Intel Tigerlake support |
| 5 | |
Aamir Bohra | a23e0c9 | 2020-03-25 15:31:12 +0530 | [diff] [blame] | 6 | if SOC_INTEL_TIGERLAKE |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
| 10 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Angel Pons | a32df26 | 2020-09-25 10:20:11 +0200 | [diff] [blame] | 11 | select ARCH_ALL_STAGES_X86_32 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 12 | select BOOT_DEVICE_SUPPORTS_WRITES |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 13 | select CACHE_MRC_SETTINGS |
Alex Levin | f3668fc | 2020-06-11 20:09:45 -0700 | [diff] [blame] | 14 | select CPU_INTEL_COMMON |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 15 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Michael Niewöhner | fe6070f | 2020-10-04 15:16:04 +0200 | [diff] [blame] | 16 | select CPU_SUPPORTS_PM_TIMER_EMULATION |
Duncan Laurie | 2e9315c | 2020-10-27 10:29:16 -0700 | [diff] [blame] | 17 | select DRIVERS_USB_ACPI |
Furquan Shaikh | ba75c4c | 2020-11-22 15:45:54 -0800 | [diff] [blame] | 18 | select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW |
Karthikeyan Ramasubramanian | 6abee84 | 2020-06-16 23:29:28 -0600 | [diff] [blame] | 19 | select FSP_COMPRESS_FSP_S_LZ4 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 20 | select FSP_M_XIP |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 21 | select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 22 | select GENERIC_GPIO_LIB |
| 23 | select HAVE_FSP_GOP |
| 24 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
| 25 | select HAVE_SMI_HANDLER |
| 26 | select IDT_IN_EVERY_STAGE |
Shreesh Chhabbi | 42b1d3f | 2020-11-05 12:06:29 -0800 | [diff] [blame] | 27 | select USE_CAR_NEM_ENHANCED_V1 if !INTEL_CAR_NEM |
| 28 | select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 29 | select INTEL_GMA_ACPI |
| 30 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
| 31 | select IOAPIC |
| 32 | select MRC_SETTINGS_PROTECT |
| 33 | select PARALLEL_MP |
| 34 | select PARALLEL_MP_AP_WORK |
| 35 | select MICROCODE_BLOB_UNDISCLOSED |
Subrata Banik | b622d4b | 2020-05-26 18:33:22 +0530 | [diff] [blame] | 36 | select PLATFORM_USES_FSP2_2 |
Jonathan Zhang | 01e3855 | 2020-06-17 16:03:18 -0700 | [diff] [blame] | 37 | select FSP_PEIM_TO_PEIM_INTERFACE |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 38 | select REG_SCRIPT |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 39 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
Subrata Banik | 0359d9d | 2020-09-28 18:43:47 +0530 | [diff] [blame] | 40 | select PMC_LOW_POWER_MODE_PROGRAM |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 41 | select SOC_INTEL_COMMON |
| 42 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
| 43 | select SOC_INTEL_COMMON_BLOCK |
| 44 | select SOC_INTEL_COMMON_BLOCK_ACPI |
Subrata Banik | 21974ab | 2020-10-31 21:40:43 +0530 | [diff] [blame] | 45 | select SOC_INTEL_COMMON_BLOCK_CAR |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 46 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
Furquan Shaikh | 23e8813 | 2020-10-08 23:44:20 -0700 | [diff] [blame] | 47 | select SOC_INTEL_COMMON_BLOCK_CNVI |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 48 | select SOC_INTEL_COMMON_BLOCK_CPU |
| 49 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
Tim Wawrzynczak | c5316ec | 2020-05-29 15:20:56 -0600 | [diff] [blame] | 50 | select SOC_INTEL_COMMON_BLOCK_DTT |
Nick Vaccaro | ef8258a | 2019-12-09 22:11:33 -0800 | [diff] [blame] | 51 | select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT |
Duncan Laurie | 7d97136 | 2020-11-05 10:09:58 -0800 | [diff] [blame] | 52 | select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 53 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
| 54 | select SOC_INTEL_COMMON_BLOCK_HDA |
Duncan Laurie | e997d85 | 2020-10-10 00:18:08 +0000 | [diff] [blame] | 55 | select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 56 | select SOC_INTEL_COMMON_BLOCK_SA |
| 57 | select SOC_INTEL_COMMON_BLOCK_SMM |
| 58 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP |
Duncan Laurie | 6f58b99 | 2020-08-28 19:44:42 +0000 | [diff] [blame] | 59 | select SOC_INTEL_COMMON_BLOCK_USB4 |
| 60 | select SOC_INTEL_COMMON_BLOCK_USB4_PCIE |
Duncan Laurie | 2e9315c | 2020-10-27 10:29:16 -0700 | [diff] [blame] | 61 | select SOC_INTEL_COMMON_BLOCK_USB4_XHCI |
Karthikeyan Ramasubramanian | fa9e8f9 | 2020-11-04 22:22:46 -0700 | [diff] [blame] | 62 | select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 63 | select SOC_INTEL_COMMON_FSP_RESET |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 64 | select SOC_INTEL_COMMON_PCH_BASE |
| 65 | select SOC_INTEL_COMMON_RESET |
Sumeet R Pawnikar | d213246 | 2020-05-15 15:55:37 +0530 | [diff] [blame] | 66 | select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 67 | select SSE2 |
| 68 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 69 | select TSC_MONOTONIC_TIMER |
| 70 | select UDELAY_TSC |
| 71 | select UDK_2017_BINDING |
| 72 | select DISPLAY_FSP_VERSION_INFO |
| 73 | select HECI_DISABLE_USING_SMM |
| 74 | |
| 75 | config DCACHE_RAM_BASE |
| 76 | default 0xfef00000 |
| 77 | |
| 78 | config DCACHE_RAM_SIZE |
Maulik V Vaghela | e9b1e0f | 2019-12-16 16:39:53 +0530 | [diff] [blame] | 79 | default 0x80000 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 80 | help |
| 81 | The size of the cache-as-ram region required during bootblock |
| 82 | and/or romstage. |
| 83 | |
| 84 | config DCACHE_BSP_STACK_SIZE |
| 85 | hex |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 86 | default 0x40400 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 87 | help |
| 88 | The amount of anticipated stack usage in CAR by bootblock and |
| 89 | other stages. In the case of FSP_USES_CB_STACK default value will be |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 90 | sum of FSP-M stack requirement(256KiB) and CB romstage stack requirement |
| 91 | (~1KiB). |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 92 | |
| 93 | config FSP_TEMP_RAM_SIZE |
| 94 | hex |
Maulik V Vaghela | e9b1e0f | 2019-12-16 16:39:53 +0530 | [diff] [blame] | 95 | default 0x20000 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 96 | help |
| 97 | The amount of anticipated heap usage in CAR by FSP. |
| 98 | Refer to Platform FSP integration guide document to know |
| 99 | the exact FSP requirement for Heap setup. |
| 100 | |
Duncan Laurie | a5bb31f | 2020-07-29 16:31:18 -0700 | [diff] [blame] | 101 | config CHIPSET_DEVICETREE |
| 102 | string |
| 103 | default "soc/intel/tigerlake/chipset.cb" |
| 104 | |
Furquan Shaikh | ba75c4c | 2020-11-22 15:45:54 -0800 | [diff] [blame] | 105 | config EXT_BIOS_WIN_BASE |
| 106 | default 0xf8000000 |
| 107 | |
| 108 | config EXT_BIOS_WIN_SIZE |
| 109 | default 0x2000000 |
| 110 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 111 | config IFD_CHIPSET |
| 112 | string |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 113 | default "tgl" |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 114 | |
| 115 | config IED_REGION_SIZE |
| 116 | hex |
| 117 | default 0x400000 |
| 118 | |
| 119 | config HEAP_SIZE |
| 120 | hex |
Duncan Laurie | aab226c | 2020-06-08 17:36:21 -0700 | [diff] [blame] | 121 | default 0x10000 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 122 | |
| 123 | config MAX_ROOT_PORTS |
| 124 | int |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 125 | default 12 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 126 | |
Ravi Sarawadi | 2fd4972 | 2019-12-16 23:41:36 -0800 | [diff] [blame] | 127 | config MAX_PCIE_CLOCKS |
| 128 | int |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 129 | default 7 |
Ravi Sarawadi | 2fd4972 | 2019-12-16 23:41:36 -0800 | [diff] [blame] | 130 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 131 | config SMM_TSEG_SIZE |
| 132 | hex |
| 133 | default 0x800000 |
| 134 | |
| 135 | config SMM_RESERVED_SIZE |
| 136 | hex |
| 137 | default 0x200000 |
| 138 | |
| 139 | config PCR_BASE_ADDRESS |
| 140 | hex |
| 141 | default 0xfd000000 |
| 142 | help |
| 143 | This option allows you to select MMIO Base Address of sideband bus. |
| 144 | |
| 145 | config MMCONF_BASE_ADDRESS |
| 146 | hex |
| 147 | default 0xc0000000 |
| 148 | |
| 149 | config CPU_BCLK_MHZ |
| 150 | int |
| 151 | default 100 |
| 152 | |
| 153 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
| 154 | int |
| 155 | default 120 |
| 156 | |
Michael Niewöhner | dadcbfb | 2020-10-04 14:48:05 +0200 | [diff] [blame] | 157 | config CPU_XTAL_HZ |
| 158 | default 38400000 |
| 159 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 160 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 161 | int |
| 162 | default 133 |
| 163 | |
| 164 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 165 | int |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 166 | default 4 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 167 | |
| 168 | config SOC_INTEL_I2C_DEV_MAX |
| 169 | int |
| 170 | default 6 |
| 171 | |
| 172 | config SOC_INTEL_UART_DEV_MAX |
| 173 | int |
| 174 | default 3 |
| 175 | |
| 176 | config CONSOLE_UART_BASE_ADDRESS |
| 177 | hex |
Bora Guvendik | c3c3e45 | 2020-11-13 21:35:19 -0800 | [diff] [blame] | 178 | default 0xfe03e000 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 179 | depends on INTEL_LPSS_UART_FOR_CONSOLE |
| 180 | |
| 181 | # Clock divider parameters for 115200 baud rate |
Ravi Sarawadi | 3838701 | 2019-12-19 15:04:58 -0800 | [diff] [blame] | 182 | # Baudrate = (UART source clcok * M) /(N *16) |
| 183 | # TGL UART source clock: 120MHz |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 184 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 185 | hex |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 186 | default 0x25a |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 187 | |
| 188 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 189 | hex |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 190 | default 0x7fff |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 191 | |
| 192 | config CHROMEOS |
| 193 | select CHROMEOS_RAMOOPS_DYNAMIC |
| 194 | |
Jes Klinke | e046b71 | 2020-08-19 14:01:30 -0700 | [diff] [blame] | 195 | # Tiger Lake SoC requires at least 100us interrupt pulses in order to guarantee detection |
| 196 | # in all low power states. Cr50 TPM, if used, needs to be told to generate longer pulses. |
| 197 | config TPM_CR50 |
| 198 | select CR50_USE_LONG_INTERRUPT_PULSES |
| 199 | |
Srinidhi N Kaushik | 74c16d0 | 2020-11-04 11:29:33 -0800 | [diff] [blame] | 200 | config VBT_DATA_SIZE_KB |
| 201 | int |
| 202 | default 9 |
| 203 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 204 | config VBOOT |
| 205 | select VBOOT_SEPARATE_VERSTAGE |
| 206 | select VBOOT_MUST_REQUEST_DISPLAY |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 207 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 208 | select VBOOT_VBNV_CMOS |
| 209 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| 210 | |
| 211 | config C_ENV_BOOTBLOCK_SIZE |
| 212 | hex |
| 213 | default 0xC000 |
| 214 | |
| 215 | config CBFS_SIZE |
| 216 | hex |
| 217 | default 0x200000 |
| 218 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 219 | config FSP_HEADER_PATH |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 220 | default "src/vendorcode/intel/fsp/fsp2_0/tigerlake/" |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 221 | |
| 222 | config FSP_FD_PATH |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 223 | default "3rdparty/fsp/TigerLakeFspBinPkg/Fsp.fd" |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 224 | |
Subrata Banik | 56626cf | 2020-02-27 19:39:22 +0530 | [diff] [blame] | 225 | config SOC_INTEL_TIGERLAKE_DEBUG_CONSENT |
| 226 | int "Debug Consent for TGL" |
| 227 | # USB DBC is more common for developers so make this default to 3 if |
| 228 | # SOC_INTEL_DEBUG_CONSENT=y |
| 229 | default 3 if SOC_INTEL_DEBUG_CONSENT |
| 230 | default 0 |
| 231 | help |
| 232 | This is to control debug interface on SOC. |
| 233 | Setting non-zero value will allow to use DBC or DCI to debug SOC. |
| 234 | PlatformDebugConsent in FspmUpd.h has the details. |
| 235 | |
| 236 | Desired platform debug type are |
| 237 | 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), |
| 238 | 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), |
| 239 | 6:Enable (2-wire DCI OOB), 7:Manual |
Subrata Banik | ebf1daa | 2020-05-19 12:32:41 +0530 | [diff] [blame] | 240 | |
| 241 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 242 | hex |
Anil Kumar | 033038f | 2020-09-08 16:18:45 -0700 | [diff] [blame] | 243 | default 0x2000 |
Brandon Breitenstein | 99b38a9 | 2019-12-19 23:12:58 -0800 | [diff] [blame] | 244 | |
| 245 | config EARLY_TCSS_DISPLAY |
| 246 | bool "Enable early TCSS display" |
| 247 | depends on RUN_FSP_GOP |
| 248 | help |
| 249 | Enable displays to be detected over Type-C ports during boot. |
| 250 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 251 | endif |