Angel Pons | f94ac9a | 2020-04-05 15:46:48 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 2 | |
Angel Pons | 2ead363 | 2020-09-24 16:50:05 +0200 | [diff] [blame] | 3 | /* Use simple device model for this file even in ramstage */ |
Kyösti Mälkki | 326edeb | 2019-07-24 13:27:46 +0300 | [diff] [blame] | 4 | #define __SIMPLE_DEVICE__ |
| 5 | |
Angel Pons | 7fa445e | 2020-10-13 21:14:32 +0200 | [diff] [blame] | 6 | #include <arch/romstage.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 7 | #include <cbmem.h> |
Kyösti Mälkki | 8f09688d | 2019-08-15 11:29:15 +0300 | [diff] [blame] | 8 | #include <cpu/x86/smm.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 9 | #include <device/pci.h> |
Kyösti Mälkki | 26a682c | 2019-08-02 06:13:22 +0300 | [diff] [blame] | 10 | #include <device/pci_ops.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 11 | #include <soc/pci_devs.h> |
| 12 | #include <soc/systemagent.h> |
Kyösti Mälkki | 26a682c | 2019-08-02 06:13:22 +0300 | [diff] [blame] | 13 | #include <stdint.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 14 | |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 15 | static uintptr_t dpr_region_start(void) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 16 | { |
| 17 | /* |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 18 | * Base of DPR is top of usable DRAM below 4GiB. The register has |
| 19 | * 1 MiB alignment and reports the TOP of the range, the base |
| 20 | * must be calculated from the size in MiB in bits 11:4. |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 21 | */ |
Angel Pons | 29924b2 | 2021-06-15 13:55:03 +0200 | [diff] [blame] | 22 | uintptr_t dpr = pci_read_config32(HOST_BRIDGE, DPR); |
Elyes HAOUAS | 694cbc0 | 2020-08-29 18:11:16 +0200 | [diff] [blame] | 23 | uintptr_t tom = ALIGN_DOWN(dpr, 1 * MiB); |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 24 | |
| 25 | /* Subtract DMA Protected Range size if enabled */ |
| 26 | if (dpr & DPR_EPM) |
| 27 | tom -= (dpr & DPR_SIZE_MASK) << 16; |
| 28 | |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 29 | return tom; |
| 30 | } |
| 31 | |
Elyes Haouas | 799c321 | 2022-11-09 14:00:44 +0100 | [diff] [blame] | 32 | uintptr_t cbmem_top_chipset(void) |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 33 | { |
Elyes Haouas | 799c321 | 2022-11-09 14:00:44 +0100 | [diff] [blame] | 34 | return dpr_region_start(); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 35 | } |
Kyösti Mälkki | 26a682c | 2019-08-02 06:13:22 +0300 | [diff] [blame] | 36 | |
Kyösti Mälkki | 8f09688d | 2019-08-15 11:29:15 +0300 | [diff] [blame] | 37 | void smm_region(uintptr_t *start, size_t *size) |
Kyösti Mälkki | 26a682c | 2019-08-02 06:13:22 +0300 | [diff] [blame] | 38 | { |
Angel Pons | 29924b2 | 2021-06-15 13:55:03 +0200 | [diff] [blame] | 39 | uintptr_t tseg = pci_read_config32(HOST_BRIDGE, TSEG); |
| 40 | uintptr_t bgsm = pci_read_config32(HOST_BRIDGE, BGSM); |
Kyösti Mälkki | 26a682c | 2019-08-02 06:13:22 +0300 | [diff] [blame] | 41 | |
Kyösti Mälkki | 8f09688d | 2019-08-15 11:29:15 +0300 | [diff] [blame] | 42 | tseg = ALIGN_DOWN(tseg, 1 * MiB); |
| 43 | bgsm = ALIGN_DOWN(bgsm, 1 * MiB); |
| 44 | *start = tseg; |
| 45 | *size = bgsm - tseg; |
Kyösti Mälkki | 26a682c | 2019-08-02 06:13:22 +0300 | [diff] [blame] | 46 | } |
Angel Pons | 7fa445e | 2020-10-13 21:14:32 +0200 | [diff] [blame] | 47 | |
| 48 | void fill_postcar_frame(struct postcar_frame *pcf) |
| 49 | { |
| 50 | uintptr_t top_of_ram; |
| 51 | |
| 52 | /* Cache at least 8 MiB below the top of ram, and at most 8 MiB |
| 53 | * above top of the ram. This satisfies MTRR alignment requirement |
| 54 | * with different TSEG size configurations. |
| 55 | */ |
| 56 | top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); |
| 57 | postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, |
| 58 | MTRR_TYPE_WRBACK); |
| 59 | } |