CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEM
The name was always obscure and confusing. Instead define cbmem_top()
directly in the chipset code for x86 like on ARMs.
TODO: Check TSEG alignment, it used for MTRR programming.
Change-Id: Ibbe5f05ab9c7d87d09caa673766cd17d192cd045
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7888
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c
index 046cc1d..28f4062 100644
--- a/src/soc/intel/broadwell/memmap.c
+++ b/src/soc/intel/broadwell/memmap.c
@@ -23,19 +23,24 @@
#include <broadwell/pci_devs.h>
#include <broadwell/systemagent.h>
-unsigned long get_top_of_ram(void)
+static uintptr_t dpr_region_start(void)
{
/*
* Base of DPR is top of usable DRAM below 4GiB. The register has
* 1 MiB alignment and reports the TOP of the range, the base
* must be calculated from the size in MiB in bits 11:4.
*/
- u32 dpr = pci_read_config32(SA_DEV_ROOT, DPR);
- u32 tom = dpr & ~((1 << 20) - 1);
+ uintptr_t dpr = pci_read_config32(SA_DEV_ROOT, DPR);
+ uintptr_t tom = dpr & ~((1 << 20) - 1);
/* Subtract DMA Protected Range size if enabled */
if (dpr & DPR_EPM)
tom -= (dpr & DPR_SIZE_MASK) << 16;
- return (unsigned long)tom;
+ return tom;
+}
+
+void *cbmem_top(void)
+{
+ return (void *) dpr_region_start();
}