Patrick Georgi | ea063cb | 2020-05-08 19:28:13 +0200 | [diff] [blame] | 1 | /* ifdtool - dump Intel Firmware Descriptor information */ |
Patrick Georgi | 7333a11 | 2020-05-08 20:48:04 +0200 | [diff] [blame] | 2 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | 1c795ad1 | 2011-10-14 12:49:41 -0700 | [diff] [blame] | 3 | |
| 4 | #include <stdint.h> |
Bill XIE | b3e15a2 | 2017-09-07 18:34:50 +0800 | [diff] [blame] | 5 | #include <stdbool.h> |
Duncan Laurie | 1f7fd72 | 2015-06-22 11:14:48 -0700 | [diff] [blame] | 6 | #define IFDTOOL_VERSION "1.2" |
| 7 | |
| 8 | enum ifd_version { |
| 9 | IFD_VERSION_1, |
Patrick Rudolph | 1659874 | 2022-10-21 15:13:43 +0200 | [diff] [blame] | 10 | IFD_VERSION_1_5, |
Duncan Laurie | 1f7fd72 | 2015-06-22 11:14:48 -0700 | [diff] [blame] | 11 | IFD_VERSION_2, |
| 12 | }; |
Stefan Reinauer | 1c795ad1 | 2011-10-14 12:49:41 -0700 | [diff] [blame] | 13 | |
Bill XIE | b3e15a2 | 2017-09-07 18:34:50 +0800 | [diff] [blame] | 14 | /* port from flashrom */ |
| 15 | enum ich_chipset { |
| 16 | CHIPSET_ICH_UNKNOWN, |
Bill XIE | b3e15a2 | 2017-09-07 18:34:50 +0800 | [diff] [blame] | 17 | CHIPSET_ICH8, |
| 18 | CHIPSET_ICH9, |
| 19 | CHIPSET_ICH10, |
Subrata Banik | 89db225 | 2020-08-26 14:49:17 +0530 | [diff] [blame] | 20 | CHIPSET_PCH_UNKNOWN, |
Bill XIE | b3e15a2 | 2017-09-07 18:34:50 +0800 | [diff] [blame] | 21 | CHIPSET_5_SERIES_IBEX_PEAK, |
| 22 | CHIPSET_6_SERIES_COUGAR_POINT, |
| 23 | CHIPSET_7_SERIES_PANTHER_POINT, |
| 24 | CHIPSET_8_SERIES_LYNX_POINT, |
| 25 | CHIPSET_BAYTRAIL, /* Actually all with Silvermont architecture: |
| 26 | * Bay Trail, Avoton/Rangeley |
| 27 | */ |
| 28 | CHIPSET_8_SERIES_LYNX_POINT_LP, |
| 29 | CHIPSET_8_SERIES_WELLSBURG, |
| 30 | CHIPSET_9_SERIES_WILDCAT_POINT, |
| 31 | CHIPSET_9_SERIES_WILDCAT_POINT_LP, |
Subrata Banik | 8c082e5 | 2021-06-10 23:02:29 +0530 | [diff] [blame] | 32 | CHIPSET_N_J_SERIES_APOLLO_LAKE, /* Apollo Lake: N3xxx, J3xxx */ |
| 33 | CHIPSET_N_J_SERIES_GEMINI_LAKE, /* Gemini Lake: N5xxx, J5xxx, N4xxx, J4xxx */ |
| 34 | CHIPSET_N_SERIES_JASPER_LAKE, /* Jasper Lake: N6xxx, N51xx, N45xx */ |
| 35 | CHIPSET_x6000_SERIES_ELKHART_LAKE, /* Elkhart Lake: x6000 */ |
Subrata Banik | 89db225 | 2020-08-26 14:49:17 +0530 | [diff] [blame] | 36 | CHIPSET_100_200_SERIES_SUNRISE_POINT, /* 6th-7th gen Core i/o (LP) variants */ |
Subrata Banik | 8c082e5 | 2021-06-10 23:02:29 +0530 | [diff] [blame] | 37 | CHIPSET_300_SERIES_CANNON_POINT, /* 8th-9th gen Core i/o (LP) variants */ |
| 38 | CHIPSET_400_SERIES_ICE_POINT, /* 10th gen Core i/o (LP) variants */ |
Subrata Banik | a5f4781 | 2020-09-29 11:43:01 +0530 | [diff] [blame] | 39 | CHIPSET_500_600_SERIES_TIGER_ALDER_POINT, /* 11th-12th gen Core i/o (LP) |
| 40 | * variants onwards */ |
Bill XIE | b3e15a2 | 2017-09-07 18:34:50 +0800 | [diff] [blame] | 41 | CHIPSET_C620_SERIES_LEWISBURG, |
Jeff Daly | abd4b96 | 2022-01-06 00:52:30 -0500 | [diff] [blame] | 42 | CHIPSET_DENVERTON, |
Bill XIE | b3e15a2 | 2017-09-07 18:34:50 +0800 | [diff] [blame] | 43 | }; |
| 44 | |
Andrey Petrov | 96ecb77 | 2016-10-31 19:31:54 -0700 | [diff] [blame] | 45 | enum platform { |
Furquan Shaikh | c0257dd | 2018-05-02 23:29:04 -0700 | [diff] [blame] | 46 | PLATFORM_APL, |
| 47 | PLATFORM_CNL, |
Johnny Lin | e273a02 | 2021-06-22 11:26:46 +0800 | [diff] [blame] | 48 | PLATFORM_LBG, |
Lean Sheng Tan | 0faba3c | 2021-06-09 07:52:24 -0700 | [diff] [blame] | 49 | PLATFORM_EHL, |
Furquan Shaikh | c0257dd | 2018-05-02 23:29:04 -0700 | [diff] [blame] | 50 | PLATFORM_GLK, |
Aamir Bohra | 1018be2 | 2018-06-29 15:08:50 +0530 | [diff] [blame] | 51 | PLATFORM_ICL, |
rkanabar | d64b046 | 2019-08-30 11:40:08 +0530 | [diff] [blame] | 52 | PLATFORM_JSL, |
Furquan Shaikh | 088b6e8 | 2018-03-21 10:42:37 -0700 | [diff] [blame] | 53 | PLATFORM_SKLKBL, |
Ravi Sarawadi | 7d9d63b | 2019-10-22 13:45:36 -0700 | [diff] [blame] | 54 | PLATFORM_TGL, |
Subrata Banik | 46f8073 | 2020-03-14 15:01:42 +0530 | [diff] [blame] | 55 | PLATFORM_ADL, |
Wonkyu Kim | 3922aa5 | 2022-02-02 15:19:05 -0800 | [diff] [blame] | 56 | PLATFORM_IFD2, |
Jeff Daly | abd4b96 | 2022-01-06 00:52:30 -0500 | [diff] [blame] | 57 | PLATFORM_DNV, |
Subrata Banik | ca82e61 | 2022-01-20 18:51:21 +0530 | [diff] [blame] | 58 | PLATFORM_MTL, |
Patrick Rudolph | 1659874 | 2022-10-21 15:13:43 +0200 | [diff] [blame] | 59 | PLATFORM_WBG |
Andrey Petrov | 96ecb77 | 2016-10-31 19:31:54 -0700 | [diff] [blame] | 60 | }; |
| 61 | |
Chris Douglass | 03ce014 | 2014-02-26 13:30:13 -0500 | [diff] [blame] | 62 | #define LAYOUT_LINELEN 80 |
| 63 | |
Stefan Reinauer | 1c795ad1 | 2011-10-14 12:49:41 -0700 | [diff] [blame] | 64 | enum spi_frequency { |
| 65 | SPI_FREQUENCY_20MHZ = 0, |
| 66 | SPI_FREQUENCY_33MHZ = 1, |
Duncan Laurie | 1f7fd72 | 2015-06-22 11:14:48 -0700 | [diff] [blame] | 67 | SPI_FREQUENCY_48MHZ = 2, |
| 68 | SPI_FREQUENCY_50MHZ_30MHZ = 4, |
| 69 | SPI_FREQUENCY_17MHZ = 6, |
Stefan Reinauer | 1c795ad1 | 2011-10-14 12:49:41 -0700 | [diff] [blame] | 70 | }; |
| 71 | |
Subrata Banik | d16ef4d | 2020-08-26 15:53:00 +0530 | [diff] [blame] | 72 | enum spi_frequency_500_series { |
| 73 | SPI_FREQUENCY_100MHZ = 0, |
| 74 | SPI_FREQUENCY_50MHZ = 1, |
| 75 | SPI_FREQUENCY_500SERIES_33MHZ = 3, |
| 76 | SPI_FREQUENCY_25MHZ = 4, |
| 77 | SPI_FREQUENCY_14MHZ = 6, |
| 78 | }; |
| 79 | |
Subrata Banik | e5d3992 | 2020-08-26 16:01:42 +0530 | [diff] [blame] | 80 | enum espi_frequency { |
| 81 | ESPI_FREQUENCY_20MHZ = 0, |
| 82 | ESPI_FREQUENCY_24MHZ = 1, |
| 83 | ESPI_FREQUENCY_30MHZ = 2, |
| 84 | ESPI_FREQUENCY_48MHZ = 3, |
| 85 | ESPI_FREQUENCY_60MHZ = 4, |
| 86 | ESPI_FREQUENCY_17MHZ = 6, |
| 87 | }; |
| 88 | |
| 89 | enum espi_frequency_500_series { |
| 90 | ESPI_FREQUENCY_500SERIES_20MHZ = 0, |
| 91 | ESPI_FREQUENCY_500SERIES_24MHZ = 1, |
| 92 | ESPI_FREQUENCY_500SERIES_25MHZ = 2, |
| 93 | ESPI_FREQUENCY_500SERIES_48MHZ = 3, |
| 94 | ESPI_FREQUENCY_500SERIES_60MHZ = 4, |
| 95 | }; |
| 96 | |
Stefan Reinauer | 1b1309f | 2012-05-11 15:53:43 -0700 | [diff] [blame] | 97 | enum component_density { |
| 98 | COMPONENT_DENSITY_512KB = 0, |
| 99 | COMPONENT_DENSITY_1MB = 1, |
| 100 | COMPONENT_DENSITY_2MB = 2, |
| 101 | COMPONENT_DENSITY_4MB = 3, |
| 102 | COMPONENT_DENSITY_8MB = 4, |
| 103 | COMPONENT_DENSITY_16MB = 5, |
Duncan Laurie | 1f7fd72 | 2015-06-22 11:14:48 -0700 | [diff] [blame] | 104 | COMPONENT_DENSITY_32MB = 6, |
| 105 | COMPONENT_DENSITY_64MB = 7, |
| 106 | COMPONENT_DENSITY_UNUSED = 0xf |
Stefan Reinauer | 1b1309f | 2012-05-11 15:53:43 -0700 | [diff] [blame] | 107 | }; |
| 108 | |
Stefan Reinauer | 1c795ad1 | 2011-10-14 12:49:41 -0700 | [diff] [blame] | 109 | // flash descriptor |
Maximilian Brune | ab0e680 | 2023-03-05 04:34:40 +0100 | [diff] [blame] | 110 | struct __packed fdbar { |
Stefan Reinauer | 1c795ad1 | 2011-10-14 12:49:41 -0700 | [diff] [blame] | 111 | uint32_t flvalsig; |
| 112 | uint32_t flmap0; |
| 113 | uint32_t flmap1; |
| 114 | uint32_t flmap2; |
Subrata Banik | bd2da5a | 2020-08-26 15:43:51 +0530 | [diff] [blame] | 115 | uint32_t flmap3; // Exist for 500 series onwards |
Maximilian Brune | ab0e680 | 2023-03-05 04:34:40 +0100 | [diff] [blame] | 116 | }; |
Stefan Reinauer | 1c795ad1 | 2011-10-14 12:49:41 -0700 | [diff] [blame] | 117 | |
| 118 | // regions |
Jeff Daly | 3623eca | 2022-01-05 23:51:40 -0500 | [diff] [blame] | 119 | #define MAX_REGIONS 16 |
Duncan Laurie | 1f7fd72 | 2015-06-22 11:14:48 -0700 | [diff] [blame] | 120 | #define MAX_REGIONS_OLD 5 |
Bill XIE | 4651d45 | 2017-09-12 11:54:48 +0800 | [diff] [blame] | 121 | |
Duncan Laurie | 7775d67 | 2019-06-06 13:39:26 -0700 | [diff] [blame] | 122 | enum flash_regions { |
| 123 | REGION_DESC, |
| 124 | REGION_BIOS, |
| 125 | REGION_ME, |
| 126 | REGION_GBE, |
| 127 | REGION_PDR, |
Jeff Daly | 3623eca | 2022-01-05 23:51:40 -0500 | [diff] [blame] | 128 | REGION_DEV_EXP1, |
| 129 | REGION_BIOS2, |
Duncan Laurie | 7775d67 | 2019-06-06 13:39:26 -0700 | [diff] [blame] | 130 | REGION_EC = 8, |
Jeff Daly | 3623eca | 2022-01-05 23:51:40 -0500 | [diff] [blame] | 131 | REGION_DEV_EXP2, |
| 132 | REGION_IE, |
| 133 | REGION_10GB_0, |
| 134 | REGION_10GB_1, |
| 135 | REGION_PTT = 15, |
Duncan Laurie | 7775d67 | 2019-06-06 13:39:26 -0700 | [diff] [blame] | 136 | }; |
| 137 | |
Maximilian Brune | ab0e680 | 2023-03-05 04:34:40 +0100 | [diff] [blame] | 138 | struct __packed frba { |
Bill XIE | 4651d45 | 2017-09-12 11:54:48 +0800 | [diff] [blame] | 139 | uint32_t flreg[MAX_REGIONS]; |
Maximilian Brune | ab0e680 | 2023-03-05 04:34:40 +0100 | [diff] [blame] | 140 | }; |
Stefan Reinauer | 1c795ad1 | 2011-10-14 12:49:41 -0700 | [diff] [blame] | 141 | |
| 142 | // component section |
Maximilian Brune | ab0e680 | 2023-03-05 04:34:40 +0100 | [diff] [blame] | 143 | struct __packed fcba { |
Stefan Reinauer | 1c795ad1 | 2011-10-14 12:49:41 -0700 | [diff] [blame] | 144 | uint32_t flcomp; |
| 145 | uint32_t flill; |
| 146 | uint32_t flpb; |
Maximilian Brune | ab0e680 | 2023-03-05 04:34:40 +0100 | [diff] [blame] | 147 | }; |
Stefan Reinauer | 1c795ad1 | 2011-10-14 12:49:41 -0700 | [diff] [blame] | 148 | |
| 149 | // pch strap |
Patrick Rudolph | 802cbee | 2020-05-25 12:18:11 +0200 | [diff] [blame] | 150 | #define MAX_PCHSTRP 1024 |
Bill XIE | 4651d45 | 2017-09-12 11:54:48 +0800 | [diff] [blame] | 151 | |
Maximilian Brune | ab0e680 | 2023-03-05 04:34:40 +0100 | [diff] [blame] | 152 | struct __packed fpsba { |
Bill XIE | 4651d45 | 2017-09-12 11:54:48 +0800 | [diff] [blame] | 153 | uint32_t pchstrp[MAX_PCHSTRP]; |
Maximilian Brune | ab0e680 | 2023-03-05 04:34:40 +0100 | [diff] [blame] | 154 | }; |
Stefan Reinauer | 1c795ad1 | 2011-10-14 12:49:41 -0700 | [diff] [blame] | 155 | |
Shawn Nematbakhsh | d2cb118 | 2015-09-10 19:07:13 -0700 | [diff] [blame] | 156 | /* |
| 157 | * WR / RD bits start at different locations within the flmstr regs, but |
| 158 | * otherwise have identical meaning. |
| 159 | */ |
| 160 | #define FLMSTR_WR_SHIFT_V1 24 |
| 161 | #define FLMSTR_WR_SHIFT_V2 20 |
| 162 | #define FLMSTR_RD_SHIFT_V1 16 |
| 163 | #define FLMSTR_RD_SHIFT_V2 8 |
| 164 | |
Stefan Reinauer | 1c795ad1 | 2011-10-14 12:49:41 -0700 | [diff] [blame] | 165 | // master |
Maximilian Brune | ab0e680 | 2023-03-05 04:34:40 +0100 | [diff] [blame] | 166 | struct __packed fmba { |
Stefan Reinauer | 1c795ad1 | 2011-10-14 12:49:41 -0700 | [diff] [blame] | 167 | uint32_t flmstr1; |
| 168 | uint32_t flmstr2; |
| 169 | uint32_t flmstr3; |
Duncan Laurie | 1f7fd72 | 2015-06-22 11:14:48 -0700 | [diff] [blame] | 170 | uint32_t flmstr4; |
| 171 | uint32_t flmstr5; |
Jeff Daly | abd4b96 | 2022-01-06 00:52:30 -0500 | [diff] [blame] | 172 | uint32_t flmstr6; |
Maximilian Brune | ab0e680 | 2023-03-05 04:34:40 +0100 | [diff] [blame] | 173 | }; |
Stefan Reinauer | 1c795ad1 | 2011-10-14 12:49:41 -0700 | [diff] [blame] | 174 | |
| 175 | // processor strap |
Maximilian Brune | ab0e680 | 2023-03-05 04:34:40 +0100 | [diff] [blame] | 176 | struct __packed fmsba { |
Stefan Reinauer | 1c795ad1 | 2011-10-14 12:49:41 -0700 | [diff] [blame] | 177 | uint32_t data[8]; |
Maximilian Brune | ab0e680 | 2023-03-05 04:34:40 +0100 | [diff] [blame] | 178 | }; |
Stefan Reinauer | 1c795ad1 | 2011-10-14 12:49:41 -0700 | [diff] [blame] | 179 | |
Stefan Reinauer | 4a17d29 | 2012-09-27 12:42:15 -0700 | [diff] [blame] | 180 | // ME VSCC |
Maximilian Brune | ab0e680 | 2023-03-05 04:34:40 +0100 | [diff] [blame] | 181 | struct vscc { |
Stefan Reinauer | 4a17d29 | 2012-09-27 12:42:15 -0700 | [diff] [blame] | 182 | uint32_t jid; |
| 183 | uint32_t vscc; |
Maximilian Brune | ab0e680 | 2023-03-05 04:34:40 +0100 | [diff] [blame] | 184 | }; |
Stefan Reinauer | 1c795ad1 | 2011-10-14 12:49:41 -0700 | [diff] [blame] | 185 | |
Maximilian Brune | ab0e680 | 2023-03-05 04:34:40 +0100 | [diff] [blame] | 186 | struct vtba { |
Stefan Reinauer | 4a17d29 | 2012-09-27 12:42:15 -0700 | [diff] [blame] | 187 | // Actual number of entries specified in vtl |
Stefan Tauner | 0d22614 | 2018-08-05 18:56:53 +0200 | [diff] [blame] | 188 | /* FIXME: Rationale for the limit of 8. |
| 189 | * AFAICT it's 127, cf. flashrom's ich_descriptors_tool). */ |
Maximilian Brune | ab0e680 | 2023-03-05 04:34:40 +0100 | [diff] [blame] | 190 | struct vscc entry[8]; |
| 191 | }; |
Stefan Reinauer | 4a17d29 | 2012-09-27 12:42:15 -0700 | [diff] [blame] | 192 | |
Maximilian Brune | ab0e680 | 2023-03-05 04:34:40 +0100 | [diff] [blame] | 193 | struct region { |
Maximilian Brune | 347596a | 2023-03-05 20:55:32 +0100 | [diff] [blame] | 194 | int base, limit, size, type; |
Maximilian Brune | ab0e680 | 2023-03-05 04:34:40 +0100 | [diff] [blame] | 195 | }; |
Chris Douglass | 03ce014 | 2014-02-26 13:30:13 -0500 | [diff] [blame] | 196 | |
| 197 | struct region_name { |
Bill XIE | fa5f994 | 2017-09-12 11:22:29 +0800 | [diff] [blame] | 198 | const char *pretty; |
| 199 | const char *terse; |
Bill XIE | 1bf6506 | 2017-09-12 11:31:37 +0800 | [diff] [blame] | 200 | const char *filename; |
Mathew King | c7ddc99 | 2019-08-08 14:59:25 -0600 | [diff] [blame] | 201 | const char *fmapname; |
Chris Douglass | 03ce014 | 2014-02-26 13:30:13 -0500 | [diff] [blame] | 202 | }; |