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Patrick Georgiea063cb2020-05-08 19:28:13 +02001/* ifdtool - dump Intel Firmware Descriptor information */
Patrick Georgi7333a112020-05-08 20:48:04 +02002/* SPDX-License-Identifier: GPL-2.0-only */
Stefan Reinauer1c795ad12011-10-14 12:49:41 -07003
4#include <stdint.h>
Bill XIEb3e15a22017-09-07 18:34:50 +08005#include <stdbool.h>
Duncan Laurie1f7fd722015-06-22 11:14:48 -07006#define IFDTOOL_VERSION "1.2"
7
8enum ifd_version {
9 IFD_VERSION_1,
10 IFD_VERSION_2,
11};
Stefan Reinauer1c795ad12011-10-14 12:49:41 -070012
Bill XIEb3e15a22017-09-07 18:34:50 +080013/* port from flashrom */
14enum ich_chipset {
15 CHIPSET_ICH_UNKNOWN,
16 CHIPSET_ICH,
17 CHIPSET_ICH2345,
18 CHIPSET_ICH6,
19 CHIPSET_POULSBO, /* SCH U* */
20 CHIPSET_TUNNEL_CREEK, /* Atom E6xx */
21 CHIPSET_CENTERTON, /* Atom S1220 S1240 S1260 */
22 CHIPSET_ICH7,
23 CHIPSET_ICH8,
24 CHIPSET_ICH9,
25 CHIPSET_ICH10,
Subrata Banik89db2252020-08-26 14:49:17 +053026 CHIPSET_PCH_UNKNOWN,
Bill XIEb3e15a22017-09-07 18:34:50 +080027 CHIPSET_5_SERIES_IBEX_PEAK,
28 CHIPSET_6_SERIES_COUGAR_POINT,
29 CHIPSET_7_SERIES_PANTHER_POINT,
30 CHIPSET_8_SERIES_LYNX_POINT,
31 CHIPSET_BAYTRAIL, /* Actually all with Silvermont architecture:
32 * Bay Trail, Avoton/Rangeley
33 */
34 CHIPSET_8_SERIES_LYNX_POINT_LP,
35 CHIPSET_8_SERIES_WELLSBURG,
36 CHIPSET_9_SERIES_WILDCAT_POINT,
37 CHIPSET_9_SERIES_WILDCAT_POINT_LP,
Subrata Banik89db2252020-08-26 14:49:17 +053038 CHIPSET_N_J_SERIES, /* Gemini Lake: N5xxx, J5xxx, N4xxx, J4xxx */
39 CHIPSET_100_200_SERIES_SUNRISE_POINT, /* 6th-7th gen Core i/o (LP) variants */
40 CHIPSET_300_400_SERIES_CANNON_ICE_POINT, /* 8th-10th gen Core i/o (LP) variants */
Subrata Banika5f47812020-09-29 11:43:01 +053041 CHIPSET_500_600_SERIES_TIGER_ALDER_POINT, /* 11th-12th gen Core i/o (LP)
42 * variants onwards */
Bill XIEb3e15a22017-09-07 18:34:50 +080043 CHIPSET_C620_SERIES_LEWISBURG,
44};
45
Andrey Petrov96ecb772016-10-31 19:31:54 -070046enum platform {
Furquan Shaikhc0257dd2018-05-02 23:29:04 -070047 PLATFORM_APL,
48 PLATFORM_CNL,
49 PLATFORM_GLK,
Aamir Bohra1018be22018-06-29 15:08:50 +053050 PLATFORM_ICL,
rkanabard64b0462019-08-30 11:40:08 +053051 PLATFORM_JSL,
Furquan Shaikh088b6e82018-03-21 10:42:37 -070052 PLATFORM_SKLKBL,
Ravi Sarawadi7d9d63b2019-10-22 13:45:36 -070053 PLATFORM_TGL,
Subrata Banik46f80732020-03-14 15:01:42 +053054 PLATFORM_ADL,
Andrey Petrov96ecb772016-10-31 19:31:54 -070055};
56
Chris Douglass03ce0142014-02-26 13:30:13 -050057#define LAYOUT_LINELEN 80
58
Stefan Reinauer1c795ad12011-10-14 12:49:41 -070059enum spi_frequency {
60 SPI_FREQUENCY_20MHZ = 0,
61 SPI_FREQUENCY_33MHZ = 1,
Duncan Laurie1f7fd722015-06-22 11:14:48 -070062 SPI_FREQUENCY_48MHZ = 2,
63 SPI_FREQUENCY_50MHZ_30MHZ = 4,
64 SPI_FREQUENCY_17MHZ = 6,
Stefan Reinauer1c795ad12011-10-14 12:49:41 -070065};
66
Subrata Banikd16ef4d2020-08-26 15:53:00 +053067enum spi_frequency_500_series {
68 SPI_FREQUENCY_100MHZ = 0,
69 SPI_FREQUENCY_50MHZ = 1,
70 SPI_FREQUENCY_500SERIES_33MHZ = 3,
71 SPI_FREQUENCY_25MHZ = 4,
72 SPI_FREQUENCY_14MHZ = 6,
73};
74
Subrata Banike5d39922020-08-26 16:01:42 +053075enum espi_frequency {
76 ESPI_FREQUENCY_20MHZ = 0,
77 ESPI_FREQUENCY_24MHZ = 1,
78 ESPI_FREQUENCY_30MHZ = 2,
79 ESPI_FREQUENCY_48MHZ = 3,
80 ESPI_FREQUENCY_60MHZ = 4,
81 ESPI_FREQUENCY_17MHZ = 6,
82};
83
84enum espi_frequency_500_series {
85 ESPI_FREQUENCY_500SERIES_20MHZ = 0,
86 ESPI_FREQUENCY_500SERIES_24MHZ = 1,
87 ESPI_FREQUENCY_500SERIES_25MHZ = 2,
88 ESPI_FREQUENCY_500SERIES_48MHZ = 3,
89 ESPI_FREQUENCY_500SERIES_60MHZ = 4,
90};
91
Stefan Reinauer1b1309f2012-05-11 15:53:43 -070092enum component_density {
93 COMPONENT_DENSITY_512KB = 0,
94 COMPONENT_DENSITY_1MB = 1,
95 COMPONENT_DENSITY_2MB = 2,
96 COMPONENT_DENSITY_4MB = 3,
97 COMPONENT_DENSITY_8MB = 4,
98 COMPONENT_DENSITY_16MB = 5,
Duncan Laurie1f7fd722015-06-22 11:14:48 -070099 COMPONENT_DENSITY_32MB = 6,
100 COMPONENT_DENSITY_64MB = 7,
101 COMPONENT_DENSITY_UNUSED = 0xf
Stefan Reinauer1b1309f2012-05-11 15:53:43 -0700102};
103
Stefan Reinauer1c795ad12011-10-14 12:49:41 -0700104// flash descriptor
105typedef struct {
106 uint32_t flvalsig;
107 uint32_t flmap0;
108 uint32_t flmap1;
109 uint32_t flmap2;
Subrata Banikbd2da5a2020-08-26 15:43:51 +0530110 uint32_t flmap3; // Exist for 500 series onwards
Stefan Reinauer1c795ad12011-10-14 12:49:41 -0700111} __attribute__((packed)) fdbar_t;
112
113// regions
Duncan Laurie1f7fd722015-06-22 11:14:48 -0700114#define MAX_REGIONS 9
115#define MAX_REGIONS_OLD 5
Bill XIE4651d452017-09-12 11:54:48 +0800116
Duncan Laurie7775d672019-06-06 13:39:26 -0700117enum flash_regions {
118 REGION_DESC,
119 REGION_BIOS,
120 REGION_ME,
121 REGION_GBE,
122 REGION_PDR,
123 REGION_EC = 8,
124};
125
Stefan Reinauer1c795ad12011-10-14 12:49:41 -0700126typedef struct {
Bill XIE4651d452017-09-12 11:54:48 +0800127 uint32_t flreg[MAX_REGIONS];
Stefan Reinauer1c795ad12011-10-14 12:49:41 -0700128} __attribute__((packed)) frba_t;
129
130// component section
131typedef struct {
132 uint32_t flcomp;
133 uint32_t flill;
134 uint32_t flpb;
135} __attribute__((packed)) fcba_t;
136
137// pch strap
Patrick Rudolph802cbee2020-05-25 12:18:11 +0200138#define MAX_PCHSTRP 1024
Bill XIE4651d452017-09-12 11:54:48 +0800139
Stefan Reinauer1c795ad12011-10-14 12:49:41 -0700140typedef struct {
Bill XIE4651d452017-09-12 11:54:48 +0800141 uint32_t pchstrp[MAX_PCHSTRP];
Stefan Reinauer1c795ad12011-10-14 12:49:41 -0700142} __attribute__((packed)) fpsba_t;
143
Shawn Nematbakhshd2cb1182015-09-10 19:07:13 -0700144/*
145 * WR / RD bits start at different locations within the flmstr regs, but
146 * otherwise have identical meaning.
147 */
148#define FLMSTR_WR_SHIFT_V1 24
149#define FLMSTR_WR_SHIFT_V2 20
150#define FLMSTR_RD_SHIFT_V1 16
151#define FLMSTR_RD_SHIFT_V2 8
152
Stefan Reinauer1c795ad12011-10-14 12:49:41 -0700153// master
154typedef struct {
155 uint32_t flmstr1;
156 uint32_t flmstr2;
157 uint32_t flmstr3;
Duncan Laurie1f7fd722015-06-22 11:14:48 -0700158 uint32_t flmstr4;
159 uint32_t flmstr5;
Stefan Reinauer1c795ad12011-10-14 12:49:41 -0700160} __attribute__((packed)) fmba_t;
161
162// processor strap
163typedef struct {
164 uint32_t data[8];
165} __attribute__((packed)) fmsba_t;
166
Stefan Reinauer4a17d292012-09-27 12:42:15 -0700167// ME VSCC
168typedef struct {
169 uint32_t jid;
170 uint32_t vscc;
171} vscc_t;
Stefan Reinauer1c795ad12011-10-14 12:49:41 -0700172
Stefan Reinauer4a17d292012-09-27 12:42:15 -0700173typedef struct {
174 // Actual number of entries specified in vtl
Stefan Tauner0d226142018-08-05 18:56:53 +0200175 /* FIXME: Rationale for the limit of 8.
176 * AFAICT it's 127, cf. flashrom's ich_descriptors_tool). */
Stefan Reinauer4a17d292012-09-27 12:42:15 -0700177 vscc_t entry[8];
178} vtba_t;
179
180typedef struct {
181 int base, limit, size;
182} region_t;
Chris Douglass03ce0142014-02-26 13:30:13 -0500183
184struct region_name {
Bill XIEfa5f9942017-09-12 11:22:29 +0800185 const char *pretty;
186 const char *terse;
Bill XIE1bf65062017-09-12 11:31:37 +0800187 const char *filename;
Mathew Kingc7ddc992019-08-08 14:59:25 -0600188 const char *fmapname;
Chris Douglass03ce0142014-02-26 13:30:13 -0500189};