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Stefan Reinauer1c795ad12011-10-14 12:49:41 -07001/*
2 * ifdtool - dump Intel Firmware Descriptor information
3 *
4 * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Stefan Reinauer1c795ad12011-10-14 12:49:41 -070014 */
15
16#include <stdint.h>
Bill XIEb3e15a22017-09-07 18:34:50 +080017#include <stdbool.h>
Duncan Laurie1f7fd722015-06-22 11:14:48 -070018#define IFDTOOL_VERSION "1.2"
19
20enum ifd_version {
21 IFD_VERSION_1,
22 IFD_VERSION_2,
23};
Stefan Reinauer1c795ad12011-10-14 12:49:41 -070024
Bill XIEb3e15a22017-09-07 18:34:50 +080025/* port from flashrom */
26enum ich_chipset {
27 CHIPSET_ICH_UNKNOWN,
28 CHIPSET_ICH,
29 CHIPSET_ICH2345,
30 CHIPSET_ICH6,
31 CHIPSET_POULSBO, /* SCH U* */
32 CHIPSET_TUNNEL_CREEK, /* Atom E6xx */
33 CHIPSET_CENTERTON, /* Atom S1220 S1240 S1260 */
34 CHIPSET_ICH7,
35 CHIPSET_ICH8,
36 CHIPSET_ICH9,
37 CHIPSET_ICH10,
38 CHIPSET_5_SERIES_IBEX_PEAK,
39 CHIPSET_6_SERIES_COUGAR_POINT,
40 CHIPSET_7_SERIES_PANTHER_POINT,
41 CHIPSET_8_SERIES_LYNX_POINT,
42 CHIPSET_BAYTRAIL, /* Actually all with Silvermont architecture:
43 * Bay Trail, Avoton/Rangeley
44 */
45 CHIPSET_8_SERIES_LYNX_POINT_LP,
46 CHIPSET_8_SERIES_WELLSBURG,
47 CHIPSET_9_SERIES_WILDCAT_POINT,
48 CHIPSET_9_SERIES_WILDCAT_POINT_LP,
49 CHIPSET_100_SERIES_SUNRISE_POINT, /* also 6th/7th gen Core i/o (LP)
50 * variants
51 */
52 CHIPSET_C620_SERIES_LEWISBURG,
53};
54
Andrey Petrov96ecb772016-10-31 19:31:54 -070055enum platform {
Furquan Shaikhc0257dd2018-05-02 23:29:04 -070056 PLATFORM_APL,
57 PLATFORM_CNL,
58 PLATFORM_GLK,
Aamir Bohra1018be22018-06-29 15:08:50 +053059 PLATFORM_ICL,
Furquan Shaikh088b6e82018-03-21 10:42:37 -070060 PLATFORM_SKLKBL,
Ravi Sarawadi7d9d63b2019-10-22 13:45:36 -070061 PLATFORM_TGL,
Andrey Petrov96ecb772016-10-31 19:31:54 -070062};
63
Chris Douglass03ce0142014-02-26 13:30:13 -050064#define LAYOUT_LINELEN 80
65
Stefan Reinauer1c795ad12011-10-14 12:49:41 -070066enum spi_frequency {
67 SPI_FREQUENCY_20MHZ = 0,
68 SPI_FREQUENCY_33MHZ = 1,
Duncan Laurie1f7fd722015-06-22 11:14:48 -070069 SPI_FREQUENCY_48MHZ = 2,
70 SPI_FREQUENCY_50MHZ_30MHZ = 4,
71 SPI_FREQUENCY_17MHZ = 6,
Stefan Reinauer1c795ad12011-10-14 12:49:41 -070072};
73
Stefan Reinauer1b1309f2012-05-11 15:53:43 -070074enum component_density {
75 COMPONENT_DENSITY_512KB = 0,
76 COMPONENT_DENSITY_1MB = 1,
77 COMPONENT_DENSITY_2MB = 2,
78 COMPONENT_DENSITY_4MB = 3,
79 COMPONENT_DENSITY_8MB = 4,
80 COMPONENT_DENSITY_16MB = 5,
Duncan Laurie1f7fd722015-06-22 11:14:48 -070081 COMPONENT_DENSITY_32MB = 6,
82 COMPONENT_DENSITY_64MB = 7,
83 COMPONENT_DENSITY_UNUSED = 0xf
Stefan Reinauer1b1309f2012-05-11 15:53:43 -070084};
85
Stefan Reinauer1c795ad12011-10-14 12:49:41 -070086// flash descriptor
87typedef struct {
88 uint32_t flvalsig;
89 uint32_t flmap0;
90 uint32_t flmap1;
91 uint32_t flmap2;
Stefan Reinauer1c795ad12011-10-14 12:49:41 -070092} __attribute__((packed)) fdbar_t;
93
94// regions
Duncan Laurie1f7fd722015-06-22 11:14:48 -070095#define MAX_REGIONS 9
96#define MAX_REGIONS_OLD 5
Bill XIE4651d452017-09-12 11:54:48 +080097
Duncan Laurie7775d672019-06-06 13:39:26 -070098enum flash_regions {
99 REGION_DESC,
100 REGION_BIOS,
101 REGION_ME,
102 REGION_GBE,
103 REGION_PDR,
104 REGION_EC = 8,
105};
106
Stefan Reinauer1c795ad12011-10-14 12:49:41 -0700107typedef struct {
Bill XIE4651d452017-09-12 11:54:48 +0800108 uint32_t flreg[MAX_REGIONS];
Stefan Reinauer1c795ad12011-10-14 12:49:41 -0700109} __attribute__((packed)) frba_t;
110
111// component section
112typedef struct {
113 uint32_t flcomp;
114 uint32_t flill;
115 uint32_t flpb;
116} __attribute__((packed)) fcba_t;
117
118// pch strap
Bill XIE4651d452017-09-12 11:54:48 +0800119#define MAX_PCHSTRP 18
120
Stefan Reinauer1c795ad12011-10-14 12:49:41 -0700121typedef struct {
Bill XIE4651d452017-09-12 11:54:48 +0800122 uint32_t pchstrp[MAX_PCHSTRP];
Stefan Reinauer1c795ad12011-10-14 12:49:41 -0700123} __attribute__((packed)) fpsba_t;
124
Shawn Nematbakhshd2cb1182015-09-10 19:07:13 -0700125/*
126 * WR / RD bits start at different locations within the flmstr regs, but
127 * otherwise have identical meaning.
128 */
129#define FLMSTR_WR_SHIFT_V1 24
130#define FLMSTR_WR_SHIFT_V2 20
131#define FLMSTR_RD_SHIFT_V1 16
132#define FLMSTR_RD_SHIFT_V2 8
133
Stefan Reinauer1c795ad12011-10-14 12:49:41 -0700134// master
135typedef struct {
136 uint32_t flmstr1;
137 uint32_t flmstr2;
138 uint32_t flmstr3;
Duncan Laurie1f7fd722015-06-22 11:14:48 -0700139 uint32_t flmstr4;
140 uint32_t flmstr5;
Stefan Reinauer1c795ad12011-10-14 12:49:41 -0700141} __attribute__((packed)) fmba_t;
142
143// processor strap
144typedef struct {
145 uint32_t data[8];
146} __attribute__((packed)) fmsba_t;
147
Stefan Reinauer4a17d292012-09-27 12:42:15 -0700148// ME VSCC
149typedef struct {
150 uint32_t jid;
151 uint32_t vscc;
152} vscc_t;
Stefan Reinauer1c795ad12011-10-14 12:49:41 -0700153
Stefan Reinauer4a17d292012-09-27 12:42:15 -0700154typedef struct {
155 // Actual number of entries specified in vtl
Stefan Tauner0d226142018-08-05 18:56:53 +0200156 /* FIXME: Rationale for the limit of 8.
157 * AFAICT it's 127, cf. flashrom's ich_descriptors_tool). */
Stefan Reinauer4a17d292012-09-27 12:42:15 -0700158 vscc_t entry[8];
159} vtba_t;
160
161typedef struct {
162 int base, limit, size;
163} region_t;
Chris Douglass03ce0142014-02-26 13:30:13 -0500164
165struct region_name {
Bill XIEfa5f9942017-09-12 11:22:29 +0800166 const char *pretty;
167 const char *terse;
Bill XIE1bf65062017-09-12 11:31:37 +0800168 const char *filename;
Mathew Kingc7ddc992019-08-08 14:59:25 -0600169 const char *fmapname;
Chris Douglass03ce0142014-02-26 13:30:13 -0500170};