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Stefan Reinauer1c795ad12011-10-14 12:49:41 -07001/*
2 * ifdtool - dump Intel Firmware Descriptor information
3 *
4 * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Stefan Reinauer1c795ad12011-10-14 12:49:41 -070014 */
15
16#include <stdint.h>
Bill XIEb3e15a22017-09-07 18:34:50 +080017#include <stdbool.h>
Duncan Laurie1f7fd722015-06-22 11:14:48 -070018#define IFDTOOL_VERSION "1.2"
19
20enum ifd_version {
21 IFD_VERSION_1,
22 IFD_VERSION_2,
23};
Stefan Reinauer1c795ad12011-10-14 12:49:41 -070024
Bill XIEb3e15a22017-09-07 18:34:50 +080025/* port from flashrom */
26enum ich_chipset {
27 CHIPSET_ICH_UNKNOWN,
28 CHIPSET_ICH,
29 CHIPSET_ICH2345,
30 CHIPSET_ICH6,
31 CHIPSET_POULSBO, /* SCH U* */
32 CHIPSET_TUNNEL_CREEK, /* Atom E6xx */
33 CHIPSET_CENTERTON, /* Atom S1220 S1240 S1260 */
34 CHIPSET_ICH7,
35 CHIPSET_ICH8,
36 CHIPSET_ICH9,
37 CHIPSET_ICH10,
38 CHIPSET_5_SERIES_IBEX_PEAK,
39 CHIPSET_6_SERIES_COUGAR_POINT,
40 CHIPSET_7_SERIES_PANTHER_POINT,
41 CHIPSET_8_SERIES_LYNX_POINT,
42 CHIPSET_BAYTRAIL, /* Actually all with Silvermont architecture:
43 * Bay Trail, Avoton/Rangeley
44 */
45 CHIPSET_8_SERIES_LYNX_POINT_LP,
46 CHIPSET_8_SERIES_WELLSBURG,
47 CHIPSET_9_SERIES_WILDCAT_POINT,
48 CHIPSET_9_SERIES_WILDCAT_POINT_LP,
49 CHIPSET_100_SERIES_SUNRISE_POINT, /* also 6th/7th gen Core i/o (LP)
50 * variants
51 */
52 CHIPSET_C620_SERIES_LEWISBURG,
53};
54
Andrey Petrov96ecb772016-10-31 19:31:54 -070055enum platform {
Furquan Shaikhc0257dd2018-05-02 23:29:04 -070056 PLATFORM_APL,
57 PLATFORM_CNL,
58 PLATFORM_GLK,
Aamir Bohra1018be22018-06-29 15:08:50 +053059 PLATFORM_ICL,
Furquan Shaikh088b6e82018-03-21 10:42:37 -070060 PLATFORM_SKLKBL,
Andrey Petrov96ecb772016-10-31 19:31:54 -070061};
62
Chris Douglass03ce0142014-02-26 13:30:13 -050063#define LAYOUT_LINELEN 80
64
Stefan Reinauer1c795ad12011-10-14 12:49:41 -070065enum spi_frequency {
66 SPI_FREQUENCY_20MHZ = 0,
67 SPI_FREQUENCY_33MHZ = 1,
Duncan Laurie1f7fd722015-06-22 11:14:48 -070068 SPI_FREQUENCY_48MHZ = 2,
69 SPI_FREQUENCY_50MHZ_30MHZ = 4,
70 SPI_FREQUENCY_17MHZ = 6,
Stefan Reinauer1c795ad12011-10-14 12:49:41 -070071};
72
Stefan Reinauer1b1309f2012-05-11 15:53:43 -070073enum component_density {
74 COMPONENT_DENSITY_512KB = 0,
75 COMPONENT_DENSITY_1MB = 1,
76 COMPONENT_DENSITY_2MB = 2,
77 COMPONENT_DENSITY_4MB = 3,
78 COMPONENT_DENSITY_8MB = 4,
79 COMPONENT_DENSITY_16MB = 5,
Duncan Laurie1f7fd722015-06-22 11:14:48 -070080 COMPONENT_DENSITY_32MB = 6,
81 COMPONENT_DENSITY_64MB = 7,
82 COMPONENT_DENSITY_UNUSED = 0xf
Stefan Reinauer1b1309f2012-05-11 15:53:43 -070083};
84
Stefan Reinauer1c795ad12011-10-14 12:49:41 -070085// flash descriptor
86typedef struct {
87 uint32_t flvalsig;
88 uint32_t flmap0;
89 uint32_t flmap1;
90 uint32_t flmap2;
Stefan Reinauer1c795ad12011-10-14 12:49:41 -070091} __attribute__((packed)) fdbar_t;
92
93// regions
Duncan Laurie1f7fd722015-06-22 11:14:48 -070094#define MAX_REGIONS 9
95#define MAX_REGIONS_OLD 5
Bill XIE4651d452017-09-12 11:54:48 +080096
Duncan Laurie7775d672019-06-06 13:39:26 -070097enum flash_regions {
98 REGION_DESC,
99 REGION_BIOS,
100 REGION_ME,
101 REGION_GBE,
102 REGION_PDR,
103 REGION_EC = 8,
104};
105
Stefan Reinauer1c795ad12011-10-14 12:49:41 -0700106typedef struct {
Bill XIE4651d452017-09-12 11:54:48 +0800107 uint32_t flreg[MAX_REGIONS];
Stefan Reinauer1c795ad12011-10-14 12:49:41 -0700108} __attribute__((packed)) frba_t;
109
110// component section
111typedef struct {
112 uint32_t flcomp;
113 uint32_t flill;
114 uint32_t flpb;
115} __attribute__((packed)) fcba_t;
116
117// pch strap
Bill XIE4651d452017-09-12 11:54:48 +0800118#define MAX_PCHSTRP 18
119
Stefan Reinauer1c795ad12011-10-14 12:49:41 -0700120typedef struct {
Bill XIE4651d452017-09-12 11:54:48 +0800121 uint32_t pchstrp[MAX_PCHSTRP];
Stefan Reinauer1c795ad12011-10-14 12:49:41 -0700122} __attribute__((packed)) fpsba_t;
123
Shawn Nematbakhshd2cb1182015-09-10 19:07:13 -0700124/*
125 * WR / RD bits start at different locations within the flmstr regs, but
126 * otherwise have identical meaning.
127 */
128#define FLMSTR_WR_SHIFT_V1 24
129#define FLMSTR_WR_SHIFT_V2 20
130#define FLMSTR_RD_SHIFT_V1 16
131#define FLMSTR_RD_SHIFT_V2 8
132
Stefan Reinauer1c795ad12011-10-14 12:49:41 -0700133// master
134typedef struct {
135 uint32_t flmstr1;
136 uint32_t flmstr2;
137 uint32_t flmstr3;
Duncan Laurie1f7fd722015-06-22 11:14:48 -0700138 uint32_t flmstr4;
139 uint32_t flmstr5;
Stefan Reinauer1c795ad12011-10-14 12:49:41 -0700140} __attribute__((packed)) fmba_t;
141
142// processor strap
143typedef struct {
144 uint32_t data[8];
145} __attribute__((packed)) fmsba_t;
146
Stefan Reinauer4a17d292012-09-27 12:42:15 -0700147// ME VSCC
148typedef struct {
149 uint32_t jid;
150 uint32_t vscc;
151} vscc_t;
Stefan Reinauer1c795ad12011-10-14 12:49:41 -0700152
Stefan Reinauer4a17d292012-09-27 12:42:15 -0700153typedef struct {
154 // Actual number of entries specified in vtl
Stefan Tauner0d226142018-08-05 18:56:53 +0200155 /* FIXME: Rationale for the limit of 8.
156 * AFAICT it's 127, cf. flashrom's ich_descriptors_tool). */
Stefan Reinauer4a17d292012-09-27 12:42:15 -0700157 vscc_t entry[8];
158} vtba_t;
159
160typedef struct {
161 int base, limit, size;
162} region_t;
Chris Douglass03ce0142014-02-26 13:30:13 -0500163
164struct region_name {
Bill XIEfa5f9942017-09-12 11:22:29 +0800165 const char *pretty;
166 const char *terse;
Bill XIE1bf65062017-09-12 11:31:37 +0800167 const char *filename;
Mathew Kingc7ddc992019-08-08 14:59:25 -0600168 const char *fmapname;
Chris Douglass03ce0142014-02-26 13:30:13 -0500169};