Chris Wang | 5547c37 | 2017-10-05 21:57:16 +0800 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
Matt DeVillier | 8f42472 | 2019-11-27 22:55:43 -0600 | [diff] [blame] | 3 | # IGD Displays |
| 4 | register "gfx" = "GMA_STATIC_DISPLAYS(0)" |
| 5 | |
Chris Wang | 5547c37 | 2017-10-05 21:57:16 +0800 | [diff] [blame] | 6 | # Deep Sx states |
| 7 | register "deep_s3_enable_ac" = "0" |
Furquan Shaikh | d37107e | 2017-11-08 11:28:10 -0800 | [diff] [blame] | 8 | register "deep_s3_enable_dc" = "0" |
Chris Wang | 5547c37 | 2017-10-05 21:57:16 +0800 | [diff] [blame] | 9 | register "deep_s5_enable_ac" = "1" |
| 10 | register "deep_s5_enable_dc" = "1" |
Furquan Shaikh | 9d867af | 2017-12-03 21:45:47 -0800 | [diff] [blame] | 11 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" |
Chris Wang | 5547c37 | 2017-10-05 21:57:16 +0800 | [diff] [blame] | 12 | |
| 13 | # GPE configuration |
| 14 | # Note that GPE events called out in ASL code rely on this |
| 15 | # route. i.e. If this route changes then the affected GPE |
| 16 | # offset bits also need to be changed. |
| 17 | register "gpe0_dw0" = "GPP_B" |
| 18 | register "gpe0_dw1" = "GPP_D" |
| 19 | register "gpe0_dw2" = "GPP_E" |
| 20 | |
| 21 | # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| 22 | register "gen1_dec" = "0x00fc0801" |
| 23 | register "gen2_dec" = "0x000c0201" |
| 24 | # EC memory map range is 0x900-0x9ff |
| 25 | register "gen3_dec" = "0x00fc0901" |
| 26 | |
Seunghwan Kim | 3f0c724 | 2018-02-13 16:58:00 +0900 | [diff] [blame] | 27 | # Enable DPTF |
| 28 | register "dptf_enable" = "1" |
| 29 | |
Chris Wang | 5547c37 | 2017-10-05 21:57:16 +0800 | [diff] [blame] | 30 | # Enable S0ix |
| 31 | register "s0ix_enable" = "1" |
| 32 | |
| 33 | # FSP Configuration |
Chris Wang | 5547c37 | 2017-10-05 21:57:16 +0800 | [diff] [blame] | 34 | register "SataSalpSupport" = "0" |
| 35 | register "SataMode" = "0" |
| 36 | register "SataPortsEnable[0]" = "0" |
Chris Wang | 5547c37 | 2017-10-05 21:57:16 +0800 | [diff] [blame] | 37 | register "DspEnable" = "1" |
| 38 | register "IoBufferOwnership" = "3" |
Chris Wang | 5547c37 | 2017-10-05 21:57:16 +0800 | [diff] [blame] | 39 | register "SsicPortEnable" = "0" |
Chris Wang | 5547c37 | 2017-10-05 21:57:16 +0800 | [diff] [blame] | 40 | register "ScsEmmcHs400Enabled" = "1" |
Chris Wang | 5547c37 | 2017-10-05 21:57:16 +0800 | [diff] [blame] | 41 | register "SkipExtGfxScan" = "1" |
Chris Wang | 5547c37 | 2017-10-05 21:57:16 +0800 | [diff] [blame] | 42 | register "HeciEnabled" = "0" |
Chris Wang | 5547c37 | 2017-10-05 21:57:16 +0800 | [diff] [blame] | 43 | register "SaGv" = "3" |
Chris Wang | 5547c37 | 2017-10-05 21:57:16 +0800 | [diff] [blame] | 44 | register "PmConfigSlpS3MinAssert" = "2" # 50ms |
| 45 | register "PmConfigSlpS4MinAssert" = "1" # 1s |
| 46 | register "PmConfigSlpSusMinAssert" = "1" # 500ms |
| 47 | register "PmConfigSlpAMinAssert" = "3" # 2s |
Chris Wang | 5547c37 | 2017-10-05 21:57:16 +0800 | [diff] [blame] | 48 | |
Chris Wang | 51de180 | 2017-11-24 13:43:50 +0800 | [diff] [blame] | 49 | # VR Slew rate setting for improving audible noise |
| 50 | register "AcousticNoiseMitigation" = "1" |
| 51 | register "FastPkgCRampDisableIa" = "1" |
| 52 | register "FastPkgCRampDisableGt" = "1" |
| 53 | register "FastPkgCRampDisableSa" = "1" |
| 54 | register "SlowSlewRateForIa" = "3" # Fast/16 |
| 55 | register "SlowSlewRateForGt" = "3" # Fast/16 |
Seunghwan Kim | 3dd88f1 | 2018-02-27 14:27:26 +0900 | [diff] [blame] | 56 | register "SlowSlewRateForSa" = "2" # Fast/8 |
| 57 | |
Chris Wang | 5547c37 | 2017-10-05 21:57:16 +0800 | [diff] [blame] | 58 | # VR Settings Configuration for 4 Domains |
| 59 | #+----------------+-------+-------+-------+-------+ |
| 60 | #| Domain/Setting | SA | IA | GTUS | GTS | |
| 61 | #+----------------+-------+-------+-------+-------+ |
| 62 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
| 63 | #| Psi2Threshold | 2A | 2A | 2A | 2A | |
| 64 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 65 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 66 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 67 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 68 | #| ImonOffset | 0 | 0 | 0 | 0 | |
| 69 | #| IccMax | 5A | 24A | 24A | 24A | |
| 70 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
| 71 | #| AcLoadline | 15 | 5.7 | 5.5 | 5.5 | |
| 72 | #| DcLoadline | 14.3 | 4.83 | 4.2 | 4.2 | |
| 73 | #+----------------+-------+-------+-------+-------+ |
| 74 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 75 | .vr_config_enable = 1, |
| 76 | .psi1threshold = VR_CFG_AMP(20), |
| 77 | .psi2threshold = VR_CFG_AMP(2), |
| 78 | .psi3threshold = VR_CFG_AMP(1), |
| 79 | .psi3enable = 1, |
| 80 | .psi4enable = 1, |
| 81 | .imon_slope = 0x0, |
| 82 | .imon_offset = 0x0, |
| 83 | .icc_max = VR_CFG_AMP(5), |
| 84 | .voltage_limit = 1520, |
| 85 | .ac_loadline = 1500, |
| 86 | .dc_loadline = 1430, |
| 87 | }" |
| 88 | |
| 89 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 90 | .vr_config_enable = 1, |
| 91 | .psi1threshold = VR_CFG_AMP(20), |
| 92 | .psi2threshold = VR_CFG_AMP(2), |
| 93 | .psi3threshold = VR_CFG_AMP(1), |
| 94 | .psi3enable = 1, |
| 95 | .psi4enable = 1, |
| 96 | .imon_slope = 0x0, |
| 97 | .imon_offset = 0x0, |
| 98 | .icc_max = VR_CFG_AMP(24), |
| 99 | .voltage_limit = 1520, |
| 100 | .ac_loadline = 570, |
| 101 | .dc_loadline = 483, |
| 102 | }" |
| 103 | |
| 104 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 105 | .vr_config_enable = 1, |
| 106 | .psi1threshold = VR_CFG_AMP(20), |
| 107 | .psi2threshold = VR_CFG_AMP(2), |
| 108 | .psi3threshold = VR_CFG_AMP(1), |
| 109 | .psi3enable = 1, |
| 110 | .psi4enable = 1, |
| 111 | .imon_slope = 0x0, |
| 112 | .imon_offset = 0x0, |
| 113 | .icc_max = VR_CFG_AMP(24), |
| 114 | .voltage_limit = 1520, |
| 115 | .ac_loadline = 550, |
| 116 | .dc_loadline = 420, |
| 117 | }" |
| 118 | |
| 119 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 120 | .vr_config_enable = 1, |
| 121 | .psi1threshold = VR_CFG_AMP(20), |
| 122 | .psi2threshold = VR_CFG_AMP(2), |
| 123 | .psi3threshold = VR_CFG_AMP(1), |
| 124 | .psi3enable = 1, |
| 125 | .psi4enable = 1, |
| 126 | .imon_slope = 0x0, |
| 127 | .imon_offset = 0x0, |
| 128 | .icc_max = VR_CFG_AMP(24), |
| 129 | .voltage_limit = 1520, |
| 130 | .ac_loadline = 550, |
| 131 | .dc_loadline = 420, |
| 132 | }" |
| 133 | |
| 134 | # Enable Root port 1. |
| 135 | register "PcieRpEnable[0]" = "1" |
| 136 | # Enable CLKREQ# |
| 137 | register "PcieRpClkReqSupport[0]" = "1" |
| 138 | # RP 1 uses SRCCLKREQ1# |
| 139 | register "PcieRpClkReqNumber[0]" = "1" |
Angel Pons | e16692e | 2020-08-03 12:54:48 +0200 | [diff] [blame] | 140 | # RP 1 uses uses CLK SRC 1 |
| 141 | register "PcieRpClkSrcNumber[0]" = "1" |
Furquan Shaikh | 9c12e90 | 2017-12-17 20:31:18 -0800 | [diff] [blame] | 142 | # RP 1, Enable Advanced Error Reporting |
| 143 | register "PcieRpAdvancedErrorReporting[0]" = "1" |
| 144 | # RP 1, Enable Latency Tolerance Reporting Mechanism |
| 145 | register "PcieRpLtrEnable[0]" = "1" |
Chris Wang | 5547c37 | 2017-10-05 21:57:16 +0800 | [diff] [blame] | 146 | |
Seunghwan Kim | 635e512 | 2018-06-14 12:39:56 +0900 | [diff] [blame] | 147 | register "usb2_ports[0]" = "USB2_PORT_LONG(OC1)" # Type-C Port 1 |
| 148 | register "usb2_ports[1]" = "USB2_PORT_SHORT(OC2)" # Type-A Port |
sh.kim | 35325e1 | 2017-12-01 16:09:50 +0900 | [diff] [blame] | 149 | register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth |
Seunghwan Kim | 635e512 | 2018-06-14 12:39:56 +0900 | [diff] [blame] | 150 | register "usb2_ports[4]" = "USB2_PORT_LONG(OC0)" # Type-C Port 2 |
sh.kim | 35325e1 | 2017-12-01 16:09:50 +0900 | [diff] [blame] | 151 | register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # H1 |
| 152 | register "usb2_ports[8]" = "USB2_PORT_SHORT(OC_SKIP)" # Camera |
Chris Wang | 5547c37 | 2017-10-05 21:57:16 +0800 | [diff] [blame] | 153 | |
Seunghwan Kim | 635e512 | 2018-06-14 12:39:56 +0900 | [diff] [blame] | 154 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 1 |
| 155 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 2 |
| 156 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port |
Seunghwan Kim | e5a9e60 | 2018-06-15 10:20:25 +0900 | [diff] [blame] | 157 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # LTE module |
Chris Wang | 5547c37 | 2017-10-05 21:57:16 +0800 | [diff] [blame] | 158 | |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 159 | # Intel Common SoC Config |
| 160 | #+-------------------+---------------------------+ |
| 161 | #| Field | Value | |
| 162 | #+-------------------+---------------------------+ |
| 163 | #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | |
| 164 | #| I2C0 | Touchscreen | |
| 165 | #| I2C1 | cr50 TPM. Early init is | |
| 166 | #| | required to set up a BAR | |
| 167 | #| | for TPM communication | |
| 168 | #| | before memory is up | |
| 169 | #| I2C2 | Trackpad | |
| 170 | #| I2C3 | Pen | |
| 171 | #| I2C4 | Camera | |
| 172 | #| I2C5 | Audio | |
Subrata Banik | c077b22 | 2019-08-01 10:50:35 +0530 | [diff] [blame] | 173 | #| pch_thermal_trip | PCH Trip Temperature | |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 174 | #+-------------------+---------------------------+ |
| 175 | register "common_soc_config" = "{ |
| 176 | .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, |
| 177 | .i2c[0] = { |
Chris Wang | 5220e5f | 2017-11-24 14:00:48 +0800 | [diff] [blame] | 178 | .speed = I2C_SPEED_FAST, |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 179 | .speed_config[0] = { |
| 180 | .speed = I2C_SPEED_FAST, |
| 181 | .scl_lcnt = 180, |
| 182 | .scl_hcnt = 90, |
| 183 | .sda_hold = 36, |
| 184 | }, |
| 185 | }, |
| 186 | .i2c[1] = { |
| 187 | .early_init = 1, |
| 188 | .speed = I2C_SPEED_FAST, |
| 189 | .speed_config[0] = { |
| 190 | .speed = I2C_SPEED_FAST, |
| 191 | .scl_lcnt = 185, |
| 192 | .scl_hcnt = 90, |
| 193 | .sda_hold = 36, |
| 194 | }, |
| 195 | }, |
| 196 | .i2c[2] = { |
| 197 | .speed = I2C_SPEED_FAST, |
| 198 | .speed_config[0] = { |
| 199 | .speed = I2C_SPEED_FAST, |
| 200 | .scl_lcnt = 190, |
| 201 | .scl_hcnt = 100, |
| 202 | .sda_hold = 36, |
| 203 | }, |
| 204 | }, |
| 205 | .i2c[3] = { |
| 206 | .speed = I2C_SPEED_FAST, |
| 207 | .speed_config[0] = { |
| 208 | .speed = I2C_SPEED_FAST, |
| 209 | .scl_lcnt = 185, |
| 210 | .scl_hcnt = 90, |
| 211 | .sda_hold = 36, |
| 212 | }, |
| 213 | }, |
| 214 | .i2c[4] = { |
| 215 | .speed = I2C_SPEED_FAST, |
| 216 | .speed_config[0] = { |
| 217 | .speed = I2C_SPEED_FAST, |
| 218 | .scl_lcnt = 190, |
| 219 | .scl_hcnt = 100, |
| 220 | .sda_hold = 36, |
| 221 | }, |
| 222 | }, |
| 223 | .i2c[5] = { |
| 224 | .speed = I2C_SPEED_FAST, |
| 225 | .speed_config[0] = { |
| 226 | .speed = I2C_SPEED_FAST, |
| 227 | .scl_lcnt = 190, |
| 228 | .scl_hcnt = 100, |
| 229 | .sda_hold = 36, |
| 230 | }, |
Chris Wang | 5220e5f | 2017-11-24 14:00:48 +0800 | [diff] [blame] | 231 | }, |
Subrata Banik | c077b22 | 2019-08-01 10:50:35 +0530 | [diff] [blame] | 232 | .pch_thermal_trip = 75, |
Chris Wang | 5220e5f | 2017-11-24 14:00:48 +0800 | [diff] [blame] | 233 | }" |
Chris Wang | 5547c37 | 2017-10-05 21:57:16 +0800 | [diff] [blame] | 234 | |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 235 | # Touch Screen |
| 236 | register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" |
| 237 | |
Chris Wang | 5547c37 | 2017-10-05 21:57:16 +0800 | [diff] [blame] | 238 | # H1 |
| 239 | register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" |
Chris Wang | 5547c37 | 2017-10-05 21:57:16 +0800 | [diff] [blame] | 240 | |
| 241 | # Trackpad |
| 242 | register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" |
| 243 | |
| 244 | # Pen |
| 245 | register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8" |
| 246 | |
| 247 | # Camera |
| 248 | register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" |
| 249 | |
| 250 | # Audio |
| 251 | register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" |
Chris Wang | 5547c37 | 2017-10-05 21:57:16 +0800 | [diff] [blame] | 252 | |
| 253 | # Must leave UART0 enabled or SD/eMMC will not work as PCI |
| 254 | register "SerialIoDevMode" = "{ |
| 255 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 256 | [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| 257 | [PchSerialIoIndexI2C2] = PchSerialIoPci, |
| 258 | [PchSerialIoIndexI2C3] = PchSerialIoPci, |
| 259 | [PchSerialIoIndexI2C4] = PchSerialIoPci, |
| 260 | [PchSerialIoIndexI2C5] = PchSerialIoPci, |
| 261 | [PchSerialIoIndexSpi0] = PchSerialIoDisabled, |
| 262 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, |
Furquan Shaikh | 8a1f095 | 2018-01-24 13:14:33 -0800 | [diff] [blame] | 263 | [PchSerialIoIndexUart0] = PchSerialIoSkipInit, |
Chris Wang | 5547c37 | 2017-10-05 21:57:16 +0800 | [diff] [blame] | 264 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, |
| 265 | [PchSerialIoIndexUart2] = PchSerialIoSkipInit, |
| 266 | }" |
| 267 | |
Chris Wang | 5547c37 | 2017-10-05 21:57:16 +0800 | [diff] [blame] | 268 | # PL2 override 15W for KBL-Y |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame] | 269 | register "power_limits_config" = "{ |
| 270 | .tdp_pl2_override = 15, |
| 271 | .psys_pmax = 45, |
| 272 | }" |
Chris Wang | 5547c37 | 2017-10-05 21:57:16 +0800 | [diff] [blame] | 273 | register "tcc_offset" = "10" # TCC of 90C |
| 274 | |
| 275 | # Use default SD card detect GPIO configuration |
Angel Pons | 6bd99f9 | 2021-02-20 00:16:47 +0100 | [diff] [blame^] | 276 | register "sdcard_cd_gpio" = "GPP_E15" |
Chris Wang | 5547c37 | 2017-10-05 21:57:16 +0800 | [diff] [blame] | 277 | |
Chris Wang | 5547c37 | 2017-10-05 21:57:16 +0800 | [diff] [blame] | 278 | device cpu_cluster 0 on |
| 279 | device lapic 0 on end |
| 280 | end |
| 281 | device domain 0 on |
| 282 | device pci 00.0 on end # Host Bridge |
| 283 | device pci 02.0 on end # Integrated Graphics Device |
Felix Singer | 9c1c009 | 2020-07-29 20:48:08 +0200 | [diff] [blame] | 284 | device pci 04.0 on end # SA thermal subsystem |
Felix Singer | 4d5c4e0 | 2020-07-29 22:28:37 +0200 | [diff] [blame] | 285 | device pci 05.0 on end # SA IMGU |
Chris Wang | 5547c37 | 2017-10-05 21:57:16 +0800 | [diff] [blame] | 286 | device pci 14.0 on end # USB xHCI |
Furquan Shaikh | 7ca4006 | 2018-04-25 17:59:09 -0700 | [diff] [blame] | 287 | device pci 14.1 on end # USB xDCI (OTG) |
Chris Wang | 5547c37 | 2017-10-05 21:57:16 +0800 | [diff] [blame] | 288 | device pci 14.2 on end # Thermal Subsystem |
Felix Singer | e218667 | 2020-07-29 23:20:52 +0200 | [diff] [blame] | 289 | device pci 14.3 on end # Camera |
Chris Wang | 94dc50e | 2017-11-28 16:33:27 +0800 | [diff] [blame] | 290 | device pci 15.0 on |
| 291 | chip drivers/i2c/hid |
| 292 | register "generic.hid" = ""SYTS7813"" |
| 293 | register "generic.desc" = ""Synaptics Touchscreen"" |
Karthikeyan Ramasubramanian | c37e1e6 | 2020-11-10 14:54:40 -0700 | [diff] [blame] | 294 | register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" |
Chris Wang | 94dc50e | 2017-11-28 16:33:27 +0800 | [diff] [blame] | 295 | register "generic.probed" = "1" |
| 296 | register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" |
| 297 | register "generic.enable_delay_ms" = "45" |
| 298 | register "generic.has_power_resource" = "1" |
| 299 | register "generic.disable_gpio_export_in_crs" = "1" |
| 300 | register "hid_desc_reg_offset" = "0x20" |
| 301 | device i2c 20 on end |
| 302 | end |
| 303 | end # I2C #0 |
Chris Wang | 5547c37 | 2017-10-05 21:57:16 +0800 | [diff] [blame] | 304 | device pci 15.1 on |
| 305 | chip drivers/i2c/tpm |
| 306 | register "hid" = ""GOOG0005"" |
| 307 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" |
| 308 | device i2c 50 on end |
| 309 | end |
| 310 | end # I2C #1 |
Seunghwan Kim | 5bf6347 | 2018-06-15 15:26:47 +0900 | [diff] [blame] | 311 | device pci 15.2 on |
| 312 | chip drivers/i2c/generic |
Gwendal Grignou | 145ef87 | 2018-07-03 14:31:31 -0700 | [diff] [blame] | 313 | register "hid" = ""STH9321"" |
Seunghwan Kim | 5bf6347 | 2018-06-15 15:26:47 +0900 | [diff] [blame] | 314 | register "name" = ""SEMTECH SX9321"" |
| 315 | register "desc" = ""SAR Proximity Sensor"" |
| 316 | register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A18_IRQ)" |
| 317 | register "device_present_gpio" = "GPP_B20" |
| 318 | device i2c 28 on end |
| 319 | end |
| 320 | end # I2C #2 |
Seunghwan Kim | 533ea7a | 2017-12-28 10:40:35 +0900 | [diff] [blame] | 321 | device pci 15.3 on |
| 322 | chip drivers/i2c/hid |
| 323 | register "generic.hid" = ""ACPI0C50"" |
| 324 | register "generic.cid" = ""PNP0C50"" |
| 325 | register "generic.desc" = ""Digitizer device"" |
| 326 | register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A22_IRQ)" |
| 327 | register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C9)" |
| 328 | register "generic.has_power_resource" = "1" |
| 329 | register "generic.disable_gpio_export_in_crs" = "1" |
| 330 | register "generic.wake" = "GPE0_DW0_21" |
| 331 | register "hid_desc_reg_offset" = "0x1" |
| 332 | device i2c 0x9 on end |
| 333 | end |
Furquan Shaikh | bb1e539 | 2018-01-11 20:29:38 -0800 | [diff] [blame] | 334 | chip drivers/generic/gpio_keys |
| 335 | register "name" = ""PENH"" |
| 336 | register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_B19)" |
| 337 | register "key.dev_name" = ""EJCT"" |
| 338 | register "key.linux_code" = "SW_PEN_INSERTED" |
| 339 | register "key.linux_input_type" = "EV_SW" |
| 340 | register "key.label" = ""pen_eject"" |
Furquan Shaikh | fa8b75f | 2020-06-26 01:19:46 -0700 | [diff] [blame] | 341 | register "key.wakeup_route" = "WAKEUP_ROUTE_DISABLED" |
Furquan Shaikh | bb1e539 | 2018-01-11 20:29:38 -0800 | [diff] [blame] | 342 | device generic 0 on end |
| 343 | end |
Seunghwan Kim | 533ea7a | 2017-12-28 10:40:35 +0900 | [diff] [blame] | 344 | end # I2C #3 |
Chris Wang | 5547c37 | 2017-10-05 21:57:16 +0800 | [diff] [blame] | 345 | device pci 16.0 on end # Management Engine Interface 1 |
| 346 | device pci 16.1 off end # Management Engine Interface 2 |
| 347 | device pci 16.2 off end # Management Engine IDE-R |
| 348 | device pci 16.3 off end # Management Engine KT Redirection |
| 349 | device pci 16.4 off end # Management Engine Interface 3 |
| 350 | device pci 17.0 off end # SATA |
| 351 | device pci 19.0 on end # UART #2 |
Naveen Manohar | 5bcb23e | 2017-11-04 04:00:12 +0530 | [diff] [blame] | 352 | device pci 19.1 on |
Naveen Manohar | 1533dfd | 2017-10-12 15:50:21 +0900 | [diff] [blame] | 353 | chip drivers/generic/max98357a |
Aamir Bohra | a1c82c5 | 2020-03-16 18:57:48 +0530 | [diff] [blame] | 354 | register "hid" = ""MX98357A"" |
Naveen Manohar | 1533dfd | 2017-10-12 15:50:21 +0900 | [diff] [blame] | 355 | register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)" |
| 356 | register "sdmode_delay" = "5" |
| 357 | device generic 0 on end |
| 358 | end |
Naveen Manohar | 5bcb23e | 2017-11-04 04:00:12 +0530 | [diff] [blame] | 359 | chip drivers/i2c/da7219 |
| 360 | register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D9_IRQ)" |
| 361 | register "btn_cfg" = "50" |
| 362 | register "mic_det_thr" = "500" |
| 363 | register "jack_ins_deb" = "20" |
| 364 | register "jack_det_rate" = ""32ms_64ms"" |
| 365 | register "jack_rem_deb" = "1" |
| 366 | register "a_d_btn_thr" = "0xa" |
| 367 | register "d_b_btn_thr" = "0x16" |
| 368 | register "b_c_btn_thr" = "0x21" |
| 369 | register "c_mic_btn_thr" = "0x3e" |
| 370 | register "btn_avg" = "4" |
| 371 | register "adc_1bit_rpt" = "1" |
| 372 | register "micbias_lvl" = "2600" |
| 373 | register "mic_amp_in_sel" = ""diff"" |
| 374 | device i2c 1A on end |
| 375 | end |
| 376 | end # I2C #5 |
Chris Wang | 36e40e4 | 2017-10-26 19:04:57 +0800 | [diff] [blame] | 377 | device pci 19.2 on |
| 378 | chip drivers/i2c/generic |
| 379 | register "hid" = ""ELAN0000"" |
| 380 | register "desc" = ""ELAN Touchpad"" |
| 381 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" |
| 382 | register "wake" = "GPE0_DW0_05" |
| 383 | device i2c 15 on end |
| 384 | end |
| 385 | end # I2C #4 |
Chris Wang | 5547c37 | 2017-10-05 21:57:16 +0800 | [diff] [blame] | 386 | device pci 1c.0 on |
Furquan Shaikh | a266d1e | 2020-10-04 12:52:54 -0700 | [diff] [blame] | 387 | chip drivers/wifi/generic |
Seunghwan Kim | df2ae96 | 2018-02-01 14:33:04 +0900 | [diff] [blame] | 388 | register "wake" = "GPE0_DW0_00" |
Chris Wang | 5547c37 | 2017-10-05 21:57:16 +0800 | [diff] [blame] | 389 | device pci 00.0 on end |
| 390 | end |
| 391 | end # PCI Express Port 1 |
| 392 | device pci 1c.1 off end # PCI Express Port 2 |
| 393 | device pci 1c.2 off end # PCI Express Port 3 |
| 394 | device pci 1c.3 off end # PCI Express Port 4 |
| 395 | device pci 1c.4 off end # PCI Express Port 5 |
| 396 | device pci 1c.5 off end # PCI Express Port 6 |
| 397 | device pci 1c.6 off end # PCI Express Port 7 |
| 398 | device pci 1c.7 off end # PCI Express Port 8 |
| 399 | device pci 1d.0 off end # PCI Express Port 9 |
| 400 | device pci 1d.1 off end # PCI Express Port 10 |
| 401 | device pci 1d.2 off end # PCI Express Port 11 |
| 402 | device pci 1d.3 off end # PCI Express Port 12 |
| 403 | device pci 1e.0 on end # UART #0 |
| 404 | device pci 1e.1 off end # UART #1 |
| 405 | device pci 1e.2 off end # GSPI #0 |
| 406 | device pci 1e.3 off end # GSPI #1 |
| 407 | device pci 1e.4 on end # eMMC |
| 408 | device pci 1e.5 off end # SDIO |
| 409 | device pci 1e.6 on end # SDCard |
| 410 | device pci 1f.0 on |
| 411 | chip ec/google/chromeec |
| 412 | device pnp 0c09.0 on end |
| 413 | end |
| 414 | end # LPC Interface |
| 415 | device pci 1f.1 on end # P2SB |
| 416 | device pci 1f.2 on end # Power Management Controller |
| 417 | device pci 1f.3 on end # Intel HDA |
| 418 | device pci 1f.4 on end # SMBus |
| 419 | device pci 1f.5 on end # PCH SPI |
| 420 | device pci 1f.6 off end # GbE |
| 421 | end |
| 422 | end |