Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
Matt DeVillier | 6d6fb6b | 2020-02-26 12:55:49 -0600 | [diff] [blame] | 3 | # Enable Panel as eDP and configure power delays |
Michael Niewöhner | 97e21d3 | 2020-12-28 00:49:33 +0100 | [diff] [blame] | 4 | register "panel_cfg" = "{ |
| 5 | .up_delay_ms = 210, // T3 |
| 6 | .down_delay_ms = 500, // T10 |
| 7 | .cycle_delay_ms = 5000, // T12 |
| 8 | .backlight_on_delay_ms = 1, // T7 |
| 9 | .backlight_off_delay_ms = 200, // T9 |
| 10 | }" |
Matt DeVillier | 6d6fb6b | 2020-02-26 12:55:49 -0600 | [diff] [blame] | 11 | |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 12 | # Enable deep Sx states |
| 13 | register "deep_s3_enable_ac" = "1" |
| 14 | register "deep_s3_enable_dc" = "1" |
| 15 | register "deep_s5_enable_ac" = "1" |
| 16 | register "deep_s5_enable_dc" = "1" |
| 17 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" |
| 18 | |
| 19 | register "eist_enable" = "1" |
| 20 | |
| 21 | # GPE configuration |
| 22 | # Note that GPE events called out in ASL code rely on this |
| 23 | # route. i.e. If this route changes then the affected GPE |
| 24 | # offset bits also need to be changed. |
| 25 | register "gpe0_dw0" = "GPP_C" |
| 26 | register "gpe0_dw1" = "GPP_D" |
| 27 | register "gpe0_dw2" = "GPP_E" |
| 28 | |
Michael Niewöhner | c5f1dc9 | 2021-04-10 22:51:15 +0200 | [diff] [blame] | 29 | register "gen1_dec" = "0x000c0681" |
| 30 | register "gen2_dec" = "0x000c1641" |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 31 | |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 32 | # Disable DPTF |
| 33 | register "dptf_enable" = "0" |
| 34 | |
| 35 | # FSP Configuration |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 36 | register "SataSalpSupport" = "1" |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 37 | |
| 38 | # The X210 has 3 SATA ports: a full SATA port, mSATA, and SATA over M.2 |
| 39 | register "SataPortsEnable[0]" = "1" |
| 40 | register "SataPortsEnable[1]" = "1" |
| 41 | register "SataPortsEnable[2]" = "1" |
| 42 | register "SataPortsDevSlp[0]" = "1" |
| 43 | register "SataPortsDevSlp[1]" = "1" |
| 44 | register "SataPortsDevSlp[2]" = "1" |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 45 | register "DspEnable" = "0" |
| 46 | register "IoBufferOwnership" = "0" |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 47 | register "SsicPortEnable" = "0" |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 48 | register "ScsEmmcHs400Enabled" = "0" |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 49 | register "SkipExtGfxScan" = "1" |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 50 | register "SaGv" = "SaGv_Enabled" |
| 51 | register "PmConfigSlpS3MinAssert" = "2" # 50ms |
| 52 | register "PmConfigSlpS4MinAssert" = "1" # 1s |
| 53 | register "PmConfigSlpSusMinAssert" = "3" # 500ms |
| 54 | register "PmConfigSlpAMinAssert" = "3" # 2s |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 55 | |
| 56 | register "serirq_mode" = "SERIRQ_CONTINUOUS" |
| 57 | |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 58 | # Enable Root Ports 3, 4 and 9 |
| 59 | register "PcieRpEnable[2]" = "1" # Ethernet controller |
| 60 | register "PcieRpClkReqSupport[2]" = "1" |
| 61 | register "PcieRpClkReqNumber[2]" = "0" |
| 62 | register "PcieRpClkSrcNumber[2]" = "0" |
| 63 | register "PcieRpAdvancedErrorReporting[2]" = "1" |
| 64 | register "PcieRpLtrEnable[2]" = "1" |
| 65 | |
| 66 | register "PcieRpEnable[3]" = "1" # Wireless controller |
| 67 | register "PcieRpClkReqSupport[3]" = "1" |
| 68 | register "PcieRpClkReqNumber[3]" = "1" |
| 69 | register "PcieRpClkSrcNumber[3]" = "1" |
| 70 | register "PcieRpAdvancedErrorReporting[3]" = "1" |
| 71 | register "PcieRpLtrEnable[3]" = "1" |
| 72 | |
| 73 | register "PcieRpEnable[8]" = "1" # NVMe controller |
Matt DeVillier | 75afc79 | 2020-02-26 13:06:01 -0600 | [diff] [blame] | 74 | register "PcieRpClkReqSupport[8]" = "1" |
| 75 | register "PcieRpClkReqNumber[8]" = "4" |
| 76 | register "PcieRpClkSrcNumber[8]" = "4" |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 77 | register "PcieRpAdvancedErrorReporting[8]" = "1" |
| 78 | register "PcieRpLtrEnable[8]" = "1" |
| 79 | |
| 80 | register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) |
| 81 | register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) |
Elyes HAOUAS | fd8de18 | 2020-03-31 21:42:02 +0200 | [diff] [blame] | 82 | register "usb2_ports[2]" = "USB2_PORT_FLEX(OC_SKIP)" # FPR |
| 83 | register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # SD |
| 84 | register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # INT |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 85 | register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) |
Matt DeVillier | 6e50849 | 2020-03-24 15:39:34 -0500 | [diff] [blame] | 86 | register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Webcam |
| 87 | register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # mPCIe / WiFi Port |
| 88 | register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # mSATA / WWAN Port |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 89 | |
| 90 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) |
Matt DeVillier | ea861ce | 2020-03-30 12:55:29 -0500 | [diff] [blame] | 91 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 92 | |
| 93 | # PL1 override 25W |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 94 | # PL2 override 44W |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame] | 95 | register "power_limits_config" = "{ |
| 96 | .tdp_pl1_override = 25, |
| 97 | .tdp_pl2_override = 44, |
| 98 | }" |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 99 | |
| 100 | # Send an extra VR mailbox command for the PS4 exit issue |
| 101 | register "SendVrMbxCmd" = "2" |
| 102 | |
Arthur Heymans | 69cd729 | 2022-11-07 13:52:11 +0100 | [diff] [blame^] | 103 | device cpu_cluster 0 on end |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 104 | device domain 0 on |
| 105 | device pci 00.0 on end # Host Bridge |
| 106 | device pci 02.0 on end # Integrated Graphics Device |
Felix Singer | 9c1c009 | 2020-07-29 20:48:08 +0200 | [diff] [blame] | 107 | device pci 04.0 on end # SA thermal subsystem |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 108 | device pci 14.0 on end # USB xHCI |
| 109 | device pci 14.1 off end # USB xDCI (OTG) |
| 110 | device pci 14.2 on end # Thermal Subsystem |
Felix Singer | e218667 | 2020-07-29 23:20:52 +0200 | [diff] [blame] | 111 | device pci 14.3 off end # Camera |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 112 | device pci 16.0 on end # Management Engine Interface 1 |
| 113 | device pci 16.1 off end # Management Engine Interface 2 |
| 114 | device pci 16.2 off end # Management Engine IDE-R |
| 115 | device pci 16.3 off end # Management Engine KT Redirection |
| 116 | device pci 16.4 off end # Management Engine Interface 3 |
| 117 | device pci 17.0 on end # SATA |
| 118 | device pci 1c.0 off end # PCI Express Port 1 |
| 119 | device pci 1c.1 off end # PCI Express Port 2 |
| 120 | device pci 1c.2 on end # PCI Express Port 3 |
| 121 | device pci 1c.3 on end # PCI Express Port 4 |
| 122 | device pci 1c.4 off end # PCI Express Port 5 |
| 123 | device pci 1c.5 off end # PCI Express Port 6 |
| 124 | device pci 1c.6 off end # PCI Express Port 7 |
| 125 | device pci 1c.7 off end # PCI Express Port 8 |
| 126 | device pci 1d.0 on end # PCI Express Port 9 |
| 127 | device pci 1d.1 off end # PCI Express Port 10 |
| 128 | device pci 1d.2 off end # PCI Express Port 11 |
| 129 | device pci 1d.3 off end # PCI Express Port 12 |
Felix Singer | 5291952 | 2020-07-29 21:44:36 +0200 | [diff] [blame] | 130 | device pci 1e.6 off end # SDXC |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 131 | device pci 1f.0 on |
| 132 | chip ec/51nb/npce985la0dx |
| 133 | device pnp 0c09.0 on end |
| 134 | device pnp 4e.5 on end |
| 135 | device pnp 4e.6 on end |
| 136 | device pnp 4e.11 on end |
| 137 | end |
| 138 | end # LPC Interface |
| 139 | device pci 1f.1 off end # P2SB |
| 140 | device pci 1f.2 on end # Power Management Controller |
| 141 | device pci 1f.3 on end # Intel HDA |
| 142 | device pci 1f.4 on end # SMBus |
| 143 | device pci 1f.5 off end # PCH SPI |
| 144 | device pci 1f.6 off end # GbE |
| 145 | end |
| 146 | end |