| Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 1 | config SOC_INTEL_COMMON_BLOCK_ACPI |
| 2 | depends on SOC_INTEL_COMMON_BLOCK_CPU |
| 3 | depends on SOC_INTEL_COMMON_BLOCK_PMC |
| Kyösti Mälkki | 69a1396 | 2023-04-08 14:10:48 +0300 | [diff] [blame^] | 4 | select ACPI_COMMON_MADT_LAPIC if !SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID |
| Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 5 | bool |
| 6 | help |
| 7 | Intel Processor common code for ACPI |
| Michael Niewöhner | 89e83b7 | 2020-11-12 23:47:30 +0100 | [diff] [blame] | 8 | |
| Angel Pons | 98f672a | 2021-02-19 19:42:10 +0100 | [diff] [blame] | 9 | config SOC_INTEL_COMMON_BLOCK_ACPI_GPIO |
| 10 | bool |
| 11 | |
| Michael Niewöhner | f0a44ae | 2021-01-01 21:04:09 +0100 | [diff] [blame] | 12 | config SOC_INTEL_COMMON_BLOCK_ACPI_LPIT |
| 13 | bool |
| 14 | depends on HAVE_ACPI_TABLES |
| 15 | select ACPI_LPIT |
| 16 | help |
| Francois Toguo | 15cbc3b | 2021-01-26 10:27:49 -0800 | [diff] [blame] | 17 | Generate LPIT table with LPI state entries |
| 18 | |
| Tim Wawrzynczak | 6424648 | 2021-06-25 22:44:45 -0600 | [diff] [blame] | 19 | config SOC_INTEL_COMMON_BLOCK_ACPI_PEP |
| 20 | bool |
| 21 | depends on HAVE_ACPI_TABLES |
| 22 | help |
| 23 | Generate an Intel Power Engine device object in the SSDT. This is |
| 24 | usually used for providing ACPI hooks for S0ix exit/entry. |
| 25 | |
| Tim Wawrzynczak | 2eb100d | 2021-07-01 08:20:17 -0600 | [diff] [blame] | 26 | config SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ |
| 27 | bool |
| 28 | depends on SOC_INTEL_COMMON_BLOCK_ACPI_PEP |
| 29 | help |
| 30 | Generate a 2nd set of _DSM functions for the Power Engine device that |
| 31 | will return a buffer that contains the contents of the PMC's LPM |
| 32 | requirements registers. A kernel can use this to display the |
| 33 | requirements for different LPM substates. |
| 34 | |
| Francois Toguo | 15cbc3b | 2021-01-26 10:27:49 -0800 | [diff] [blame] | 35 | config SOC_INTEL_COMMON_BLOCK_CRASHLOG |
| 36 | bool |
| 37 | depends on SOC_INTEL_CRASHLOG |
| 38 | help |
| 39 | Generate crash data for BERT table |
| Michael Niewöhner | f0a44ae | 2021-01-01 21:04:09 +0100 | [diff] [blame] | 40 | |
| Michael Niewöhner | 89e83b7 | 2020-11-12 23:47:30 +0100 | [diff] [blame] | 41 | if SOC_INTEL_COMMON_BLOCK_ACPI |
| 42 | |
| 43 | config SOC_INTEL_COMMON_BLOCK_ACPI_CPPC |
| 44 | bool |
| 45 | help |
| 46 | Generate CPPC entries for Intel SpeedShift |
| 47 | |
| Sridahr Siricilla | cd1cd8d | 2021-11-11 01:29:40 +0530 | [diff] [blame] | 48 | config SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID |
| 49 | bool |
| 50 | help |
| 51 | Defines hybrid CPU specific ACPI helper functions. |
| 52 | |
| Subrata Banik | a00db94 | 2022-10-12 14:24:41 +0530 | [diff] [blame] | 53 | config SOC_INTEL_UFS_OCP_TIMER_DISABLE |
| 54 | bool |
| 55 | help |
| 56 | OCP Timer need to be disabled in SCS UFS IOSF Bridge to |
| 57 | work around the Silicon Issue due to which LTR mechanism |
| 58 | doesn't work. |
| 59 | |
| Meera Ravindranath | 9e4488a | 2022-10-10 10:48:18 +0530 | [diff] [blame] | 60 | config SOC_INTEL_UFS_LTR_DISQUALIFY |
| 61 | bool |
| 62 | help |
| 63 | LTR needs to be disqualified for UFS in D3 to ensure PMC |
| 64 | ignores LTR from UFS IP which is infinite. |
| Michael Niewöhner | 89e83b7 | 2020-11-12 23:47:30 +0100 | [diff] [blame] | 65 | endif |