| commit | 89e83b76b4d50d0977345becf504a1afa0668211 | [log] [tgz] |
|---|---|---|
| author | Michael Niewöhner <foss@mniewoehner.de> | Thu Nov 12 23:47:30 2020 +0100 |
| committer | Michael Niewöhner <foss@mniewoehner.de> | Fri Nov 13 18:42:49 2020 +0000 |
| tree | 9f0f241dc399ac29d02c4bf6c263ca53ce6f3fb7 | |
| parent | 11f212b825c1f1fbeaf8e4deb052872182d3fbce [diff] [blame] |
soc/intel/common/block/acpi: add Kconfig for CPPC entries generation Change-Id: Ieae9f221ffb27cf52cab21a130e18aa3929caea3 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47540 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/common/block/acpi/Kconfig b/src/soc/intel/common/block/acpi/Kconfig index ff59172..d9a7a87 100644 --- a/src/soc/intel/common/block/acpi/Kconfig +++ b/src/soc/intel/common/block/acpi/Kconfig
@@ -4,3 +4,12 @@ bool help Intel Processor common code for ACPI + +if SOC_INTEL_COMMON_BLOCK_ACPI + +config SOC_INTEL_COMMON_BLOCK_ACPI_CPPC + bool + help + Generate CPPC entries for Intel SpeedShift + +endif