| config SOC_INTEL_COMMON_BLOCK_ACPI |
| depends on SOC_INTEL_COMMON_BLOCK_CPU |
| depends on SOC_INTEL_COMMON_BLOCK_PMC |
| select ACPI_COMMON_MADT_LAPIC if !SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID |
| bool |
| help |
| Intel Processor common code for ACPI |
| |
| config SOC_INTEL_COMMON_BLOCK_ACPI_GPIO |
| bool |
| |
| config SOC_INTEL_COMMON_BLOCK_ACPI_LPIT |
| bool |
| depends on HAVE_ACPI_TABLES |
| select ACPI_LPIT |
| help |
| Generate LPIT table with LPI state entries |
| |
| config SOC_INTEL_COMMON_BLOCK_ACPI_PEP |
| bool |
| depends on HAVE_ACPI_TABLES |
| help |
| Generate an Intel Power Engine device object in the SSDT. This is |
| usually used for providing ACPI hooks for S0ix exit/entry. |
| |
| config SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ |
| bool |
| depends on SOC_INTEL_COMMON_BLOCK_ACPI_PEP |
| help |
| Generate a 2nd set of _DSM functions for the Power Engine device that |
| will return a buffer that contains the contents of the PMC's LPM |
| requirements registers. A kernel can use this to display the |
| requirements for different LPM substates. |
| |
| config SOC_INTEL_COMMON_BLOCK_CRASHLOG |
| bool |
| depends on SOC_INTEL_CRASHLOG |
| help |
| Generate crash data for BERT table |
| |
| if SOC_INTEL_COMMON_BLOCK_ACPI |
| |
| config SOC_INTEL_COMMON_BLOCK_ACPI_CPPC |
| bool |
| help |
| Generate CPPC entries for Intel SpeedShift |
| |
| config SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID |
| bool |
| help |
| Defines hybrid CPU specific ACPI helper functions. |
| |
| config SOC_INTEL_UFS_OCP_TIMER_DISABLE |
| bool |
| help |
| OCP Timer need to be disabled in SCS UFS IOSF Bridge to |
| work around the Silicon Issue due to which LTR mechanism |
| doesn't work. |
| |
| config SOC_INTEL_UFS_LTR_DISQUALIFY |
| bool |
| help |
| LTR needs to be disqualified for UFS in D3 to ensure PMC |
| ignores LTR from UFS IP which is infinite. |
| endif |