Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 2 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 3 | /* Use simple device model for this file even in ramstage */ |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 4 | #define __SIMPLE_DEVICE__ |
| 5 | |
Kyösti Mälkki | a963acd | 2019-08-16 20:34:25 +0300 | [diff] [blame] | 6 | #include <arch/romstage.h> |
Kyösti Mälkki | cd7a70f | 2019-08-17 20:51:08 +0300 | [diff] [blame] | 7 | #include <commonlib/helpers.h> |
Kyösti Mälkki | e2e1f12 | 2019-08-09 09:34:23 +0300 | [diff] [blame] | 8 | #include <cpu/x86/mtrr.h> |
Kyösti Mälkki | 540151f | 2019-08-15 11:20:18 +0300 | [diff] [blame] | 9 | #include <cpu/x86/smm.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 10 | #include <device/pci_ops.h> |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 11 | #include <cbmem.h> |
| 12 | #include "haswell.h" |
| 13 | |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 14 | static uintptr_t smm_region_start(void) |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 15 | { |
| 16 | /* |
| 17 | * Base of TSEG is top of usable DRAM below 4GiB. The register has |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 18 | * 1 MiB alignment. |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 19 | */ |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 20 | uintptr_t tom = pci_read_config32(HOST_BRIDGE, TSEG); |
Elyes HAOUAS | 694cbc0 | 2020-08-29 18:11:16 +0200 | [diff] [blame^] | 21 | return ALIGN_DOWN(tom, 1 * MiB); |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 22 | } |
| 23 | |
Arthur Heymans | 340e4b8 | 2019-10-23 17:25:58 +0200 | [diff] [blame] | 24 | void *cbmem_top_chipset(void) |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 25 | { |
| 26 | return (void *)smm_region_start(); |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 27 | } |
Kyösti Mälkki | 825646e | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 28 | |
Kyösti Mälkki | 540151f | 2019-08-15 11:20:18 +0300 | [diff] [blame] | 29 | void smm_region(uintptr_t *start, size_t *size) |
Kyösti Mälkki | 825646e | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 30 | { |
Kyösti Mälkki | 540151f | 2019-08-15 11:20:18 +0300 | [diff] [blame] | 31 | *start = smm_region_start(); |
| 32 | *size = CONFIG_SMM_TSEG_SIZE; |
Kyösti Mälkki | 825646e | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 33 | } |
Kyösti Mälkki | e2e1f12 | 2019-08-09 09:34:23 +0300 | [diff] [blame] | 34 | |
Kyösti Mälkki | 5bc641a | 2019-08-09 09:37:49 +0300 | [diff] [blame] | 35 | void fill_postcar_frame(struct postcar_frame *pcf) |
Kyösti Mälkki | e2e1f12 | 2019-08-09 09:34:23 +0300 | [diff] [blame] | 36 | { |
Kyösti Mälkki | e2e1f12 | 2019-08-09 09:34:23 +0300 | [diff] [blame] | 37 | uintptr_t top_of_ram; |
| 38 | |
Kyösti Mälkki | e2e1f12 | 2019-08-09 09:34:23 +0300 | [diff] [blame] | 39 | /* Cache at least 8 MiB below the top of ram, and at most 8 MiB |
| 40 | * above top of the ram. This satisfies MTRR alignment requirement |
| 41 | * with different TSEG size configurations. |
| 42 | */ |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 43 | top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8 * MiB); |
| 44 | postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); |
Kyösti Mälkki | e2e1f12 | 2019-08-09 09:34:23 +0300 | [diff] [blame] | 45 | } |