intel/haswell: Move stage_cache support function
Let garbage-collection take care of stage_cache_external_region()
if it is no needed and move implementation to a suitable file already
building for needed stages.
Remove aliasing CONFIG_RESERVED_SMM_SIZE as RESERVED_SMM_SIZE.
Change-Id: Ie6fcc40fba14575e8ee058f45a1a359a05f00aca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/src/northbridge/intel/haswell/ram_calc.c b/src/northbridge/intel/haswell/ram_calc.c
index bdf54d2..3a63afc 100644
--- a/src/northbridge/intel/haswell/ram_calc.c
+++ b/src/northbridge/intel/haswell/ram_calc.c
@@ -18,6 +18,7 @@
#include <device/pci_ops.h>
#include <cbmem.h>
+#include <stage_cache.h>
#include "haswell.h"
static uintptr_t smm_region_start(void)
@@ -34,3 +35,16 @@
{
return (void *)smm_region_start();
}
+
+/* Region of SMM space is reserved for multipurpose use. It falls below
+ * the IED region and above the SMM handler. */
+#define RESERVED_SMM_OFFSET \
+ (CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE)
+
+void stage_cache_external_region(void **base, size_t *size)
+{
+ /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
+ * The top of RAM is defined to be the TSEG base address. */
+ *size = CONFIG_SMM_RESERVED_SIZE;
+ *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET);
+}