soc/intel: Use common romstage code
This provides stack guards with checking and common
entry into postcar.
The code in cpu/intel/car/romstage.c is candidate
for becoming architectural so function prototype
is moved to <arch/romstage.h>.
Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c
index b1d86db..5bc74f8 100644
--- a/src/northbridge/intel/haswell/memmap.c
+++ b/src/northbridge/intel/haswell/memmap.c
@@ -18,10 +18,10 @@
#include <arch/romstage.h>
#include <console/console.h>
+#include <commonlib/helpers.h>
#include <cpu/x86/mtrr.h>
#include <device/pci_ops.h>
#include <cbmem.h>
-#include <cpu/intel/romstage.h>
#include <stage_cache.h>
#include "haswell.h"