intel/haswell: Move platform_enter_postcar()
Do this for consistency with remaining cpu/intel sources.
Also wipe out some spurious includes.
Change-Id: I1adde58966eae9205703b87e7aa17c50e5791a85
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c
index 3a63afc..14b66a0 100644
--- a/src/northbridge/intel/haswell/memmap.c
+++ b/src/northbridge/intel/haswell/memmap.c
@@ -16,8 +16,12 @@
// Use simple device model for this file even in ramstage
#define __SIMPLE_DEVICE__
+#include <arch/cpu.h>
+#include <console/console.h>
+#include <cpu/x86/mtrr.h>
#include <device/pci_ops.h>
#include <cbmem.h>
+#include <cpu/intel/romstage.h>
#include <stage_cache.h>
#include "haswell.h"
@@ -48,3 +52,30 @@
*size = CONFIG_SMM_RESERVED_SIZE;
*base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET);
}
+
+/* platform_enter_postcar() determines the stack to use after
+ * cache-as-ram is torn down as well as the MTRR settings to use,
+ * and continues execution in postcar stage. */
+void platform_enter_postcar(void)
+{
+ struct postcar_frame pcf;
+ uintptr_t top_of_ram;
+
+ if (postcar_frame_init(&pcf, 0))
+ die("Unable to initialize postcar frame.\n");
+ /* Cache the ROM as WP just below 4GiB. */
+ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
+
+ /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
+ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
+
+ /* Cache at least 8 MiB below the top of ram, and at most 8 MiB
+ * above top of the ram. This satisfies MTRR alignment requirement
+ * with different TSEG size configurations.
+ */
+ top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
+ postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB,
+ MTRR_TYPE_WRBACK);
+
+ run_postcar_phase(&pcf);
+}