| commit | 128c104c4d3b91d3371b03840af460d776af819d | [log] [tgz] |
|---|---|---|
| author | Martin Roth <martinroth@google.com> | Fri Nov 18 09:29:03 2016 -0700 |
| committer | Martin Roth <martinroth@google.com> | Mon Nov 21 23:43:54 2016 +0100 |
| tree | bb0621ae2c90b512948ba9fee350cf42a49f4db3 | |
| parent | c6ec8dd1cb2303f7f7a71f0f494a6fc30b93dff4 [diff] [blame] |
nb/intel: Fix some spelling mistakes in comments and strings Change-Id: I4a8297397d878e38516c8df19dd311c7ef19ec06 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17478 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
diff --git a/src/northbridge/intel/haswell/ram_calc.c b/src/northbridge/intel/haswell/ram_calc.c index d51692c..d3e88f2 100644 --- a/src/northbridge/intel/haswell/ram_calc.c +++ b/src/northbridge/intel/haswell/ram_calc.c
@@ -24,7 +24,7 @@ { /* * Base of TSEG is top of usable DRAM below 4GiB. The register has - * 1 MiB alignement. + * 1 MiB alignment. */ uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); return tom & ~((1 << 20) - 1);