Arthur Heymans | 67f29e8 | 2022-04-17 10:37:13 +0200 | [diff] [blame] | 1 | if ARCH_X86 |
| 2 | |
Stefan Reinauer | 9d5e36e | 2015-04-27 13:40:16 -0700 | [diff] [blame] | 3 | config PARALLEL_MP |
Kyösti Mälkki | 41a2c73 | 2021-05-29 21:23:18 +0300 | [diff] [blame] | 4 | def_bool y |
| 5 | depends on !LEGACY_SMP_INIT |
Raul E Rangel | 99c8478 | 2021-10-08 13:10:38 -0600 | [diff] [blame] | 6 | select CPU_INFO_V2 |
Stefan Reinauer | 9d5e36e | 2015-04-27 13:40:16 -0700 | [diff] [blame] | 7 | help |
| 8 | This option uses common MP infrastructure for bringing up APs |
| 9 | in parallel. It additionally provides a more flexible mechanism |
| 10 | for sequencing the steps of bringing up the APs. |
Arthur Heymans | 48fbf2f | 2021-11-26 14:50:42 +0100 | [diff] [blame] | 11 | The code also works for just initialising the BSP in case there |
| 12 | are no APs. |
Stefan Reinauer | 9d5e36e | 2015-04-27 13:40:16 -0700 | [diff] [blame] | 13 | |
Aaron Durbin | b21e362 | 2016-12-07 00:32:19 -0600 | [diff] [blame] | 14 | config PARALLEL_MP_AP_WORK |
| 15 | def_bool n |
| 16 | depends on PARALLEL_MP |
| 17 | help |
| 18 | Allow APs to do other work after initialization instead of going |
| 19 | to sleep. |
Stefan Reinauer | 9d5e36e | 2015-04-27 13:40:16 -0700 | [diff] [blame] | 20 | |
Arthur Heymans | 56776a1 | 2022-05-19 11:31:10 +0200 | [diff] [blame] | 21 | config X86_SMM_SKIP_RELOCATION_HANDLER |
| 22 | bool |
| 23 | default n |
| 24 | depends on PARALLEL_MP && HAVE_SMI_HANDLER |
| 25 | help |
| 26 | Skip SMM relocation using a relocation handler running in SMM |
| 27 | with a stub at 0x30000. This is useful on platforms that have |
| 28 | an alternative way to set SMBASE. |
| 29 | |
Kyösti Mälkki | 41a2c73 | 2021-05-29 21:23:18 +0300 | [diff] [blame] | 30 | config LEGACY_SMP_INIT |
| 31 | bool |
| 32 | |
Subrata Banik | 64c04e0 | 2022-05-25 01:25:55 +0530 | [diff] [blame] | 33 | config DEFAULT_X2APIC |
| 34 | def_bool n |
| 35 | help |
| 36 | Allow SoC code to set LAPIC_ACCESS_MODE to X2APIC. |
| 37 | |
| 38 | config DEFAULT_X2APIC_RUNTIME |
| 39 | def_bool n |
| 40 | help |
| 41 | Allow SoC code to set LAPIC_ACCESS_MODE to X2APIC_RUNTIME. |
| 42 | |
Subrata Banik | 55d300c | 2022-07-12 11:06:15 +0000 | [diff] [blame] | 43 | config DEFAULT_X2APIC_LATE_WORKAROUND |
| 44 | def_bool n |
| 45 | help |
| 46 | Allow SoC code to set LAPIC_ACCESS_MODE to X2APIC_LATE_WORKAROUND. |
| 47 | |
Kyösti Mälkki | 176c887 | 2021-05-29 20:33:22 +0300 | [diff] [blame] | 48 | choice LAPIC_ACCESS_MODE |
| 49 | prompt "APIC operation mode" |
Subrata Banik | 64c04e0 | 2022-05-25 01:25:55 +0530 | [diff] [blame] | 50 | default X2APIC_ONLY if DEFAULT_X2APIC |
| 51 | default X2APIC_RUNTIME if DEFAULT_X2APIC_RUNTIME |
Subrata Banik | 55d300c | 2022-07-12 11:06:15 +0000 | [diff] [blame] | 52 | default X2APIC_LATE_WORKAROUND if DEFAULT_X2APIC_LATE_WORKAROUND |
Kyösti Mälkki | 176c887 | 2021-05-29 20:33:22 +0300 | [diff] [blame] | 53 | default XAPIC_ONLY |
| 54 | |
| 55 | config XAPIC_ONLY |
| 56 | prompt "Set XAPIC mode" |
| 57 | bool |
| 58 | |
| 59 | config X2APIC_ONLY |
| 60 | prompt "Set X2APIC mode" |
| 61 | bool |
| 62 | depends on PARALLEL_MP |
Kyösti Mälkki | 176c887 | 2021-05-29 20:33:22 +0300 | [diff] [blame] | 63 | |
| 64 | config X2APIC_RUNTIME |
| 65 | prompt "Support both XAPIC and X2APIC" |
| 66 | bool |
| 67 | depends on PARALLEL_MP |
Kyösti Mälkki | 176c887 | 2021-05-29 20:33:22 +0300 | [diff] [blame] | 68 | |
Subrata Banik | 2125a17 | 2022-07-12 10:55:21 +0000 | [diff] [blame] | 69 | config X2APIC_LATE_WORKAROUND |
| 70 | prompt "Use XAPIC for AP bringup, then change to X2APIC" |
| 71 | bool |
Subrata Banik | fb28799 | 2022-07-24 11:19:04 +0530 | [diff] [blame] | 72 | depends on PARALLEL_MP && MAX_CPUS < 256 |
Subrata Banik | 2125a17 | 2022-07-12 10:55:21 +0000 | [diff] [blame] | 73 | help |
| 74 | Choose this option if the platform supports dynamic switching between |
| 75 | XAPIC to X2APIC. The initial Application Processors (APs) are configured |
| 76 | in XAPIC mode at reset and later enable X2APIC as a CPU feature. |
| 77 | All access mechanisms between XAPIC (mmio) and X2APIC (msr) switches |
| 78 | at runtime when this option is enabled. |
| 79 | |
Kyösti Mälkki | 176c887 | 2021-05-29 20:33:22 +0300 | [diff] [blame] | 80 | endchoice |
| 81 | |
Patrick Georgi | 0e9a925 | 2009-10-06 20:48:07 +0000 | [diff] [blame] | 82 | config UDELAY_LAPIC |
| 83 | bool |
| 84 | default n |
| 85 | |
Aaron Durbin | fd8291c | 2013-04-29 17:18:49 -0500 | [diff] [blame] | 86 | config LAPIC_MONOTONIC_TIMER |
| 87 | def_bool n |
| 88 | depends on UDELAY_LAPIC |
Aaron Durbin | fd8291c | 2013-04-29 17:18:49 -0500 | [diff] [blame] | 89 | help |
Elyes HAOUAS | d6e9686 | 2016-08-21 10:12:15 +0200 | [diff] [blame] | 90 | Expose monotonic time using the local APIC. |
Aaron Durbin | fd8291c | 2013-04-29 17:18:49 -0500 | [diff] [blame] | 91 | |
Patrick Georgi | e135ac5 | 2012-11-20 11:53:47 +0100 | [diff] [blame] | 92 | config UDELAY_LAPIC_FIXED_FSB |
| 93 | int |
| 94 | |
Ronald G. Minnich | 669c4a9 | 2009-08-29 03:00:51 +0000 | [diff] [blame] | 95 | config UDELAY_TSC |
| 96 | bool |
| 97 | default n |
| 98 | |
Kyösti Mälkki | 0d6ddf8 | 2019-10-31 14:52:20 +0200 | [diff] [blame] | 99 | config UNKNOWN_TSC_RATE |
| 100 | bool |
| 101 | default y if LAPIC_MONOTONIC_TIMER |
Aaron Durbin | 8e73b5d | 2013-05-01 15:27:09 -0500 | [diff] [blame] | 102 | |
Aaron Durbin | e850164 | 2013-04-29 22:22:55 -0500 | [diff] [blame] | 103 | config TSC_MONOTONIC_TIMER |
| 104 | def_bool n |
| 105 | depends on UDELAY_TSC |
Aaron Durbin | e850164 | 2013-04-29 22:22:55 -0500 | [diff] [blame] | 106 | help |
| 107 | Expose monotonic time using the TSC. |
| 108 | |
Stefan Reinauer | 0db6820 | 2012-08-07 14:44:51 -0700 | [diff] [blame] | 109 | config TSC_SYNC_LFENCE |
| 110 | bool |
| 111 | default n |
| 112 | help |
| 113 | The CPU driver should select this if the CPU needs |
| 114 | to execute an lfence instruction in order to synchronize |
| 115 | rdtsc. This is true for all modern AMD CPUs. |
| 116 | |
| 117 | config TSC_SYNC_MFENCE |
| 118 | bool |
| 119 | default n |
| 120 | help |
| 121 | The CPU driver should select this if the CPU needs |
| 122 | to execute an mfence instruction in order to synchronize |
| 123 | rdtsc. This is true for all modern Intel CPUs. |
| 124 | |
Arthur Heymans | 47be2d9 | 2019-10-12 17:32:09 +0200 | [diff] [blame] | 125 | config SETUP_XIP_CACHE |
| 126 | bool |
Arthur Heymans | 47be2d9 | 2019-10-12 17:32:09 +0200 | [diff] [blame] | 127 | depends on !NO_XIP_EARLY_STAGES |
| 128 | help |
| 129 | Select this option to set up an MTRR to cache XIP stages loaded |
| 130 | from the bootblock. This is useful on platforms lacking a |
| 131 | non-eviction mode and therefore need to be careful to avoid |
| 132 | eviction. |
| 133 | |
Stefan Reinauer | 8aedcbc | 2010-12-16 23:37:17 +0000 | [diff] [blame] | 134 | config LOGICAL_CPUS |
| 135 | bool |
| 136 | default y |
| 137 | |
Kyösti Mälkki | 4d372c7 | 2019-07-08 13:48:57 +0300 | [diff] [blame] | 138 | config HAVE_SMI_HANDLER |
| 139 | bool |
| 140 | default n |
| 141 | depends on (SMM_ASEG || SMM_TSEG) |
| 142 | |
Kyösti Mälkki | 8abf66e | 2019-07-08 09:56:00 +0300 | [diff] [blame] | 143 | config NO_SMM |
Kyösti Mälkki | 4d372c7 | 2019-07-08 13:48:57 +0300 | [diff] [blame] | 144 | bool |
| 145 | default n |
| 146 | |
Kyösti Mälkki | 8abf66e | 2019-07-08 09:56:00 +0300 | [diff] [blame] | 147 | config SMM_ASEG |
Duncan Laurie | 8bb7723 | 2012-01-09 22:11:25 -0800 | [diff] [blame] | 148 | bool |
| 149 | default n |
Kyösti Mälkki | 8abf66e | 2019-07-08 09:56:00 +0300 | [diff] [blame] | 150 | depends on !NO_SMM |
| 151 | |
| 152 | config SMM_TSEG |
| 153 | bool |
| 154 | default y |
| 155 | depends on !(NO_SMM || SMM_ASEG) |
| 156 | |
Kyösti Mälkki | 894f6f8 | 2022-01-29 14:05:58 +0200 | [diff] [blame] | 157 | config SMM_LEGACY_ASEG |
| 158 | bool |
| 159 | default y if HAVE_SMI_HANDLER && SMM_ASEG && LEGACY_SMP_INIT |
| 160 | help |
| 161 | SMM support without PARALLEL_MP, to be deprecated. |
| 162 | |
Arthur Heymans | b4ba289 | 2021-10-28 16:48:36 +0200 | [diff] [blame] | 163 | if HAVE_SMI_HANDLER && !SMM_LEGACY_ASEG |
Aaron Durbin | 50a3464 | 2013-01-03 17:38:47 -0600 | [diff] [blame] | 164 | |
Raul E Rangel | d3b8393 | 2018-06-12 10:43:09 -0600 | [diff] [blame] | 165 | config SMM_MODULE_STACK_SIZE |
| 166 | hex |
Patrick Rudolph | ed8d777 | 2021-06-12 06:21:27 +0200 | [diff] [blame] | 167 | default 0x800 if ARCH_RAMSTAGE_X86_64 |
Raul E Rangel | d3b8393 | 2018-06-12 10:43:09 -0600 | [diff] [blame] | 168 | default 0x400 |
Raul E Rangel | d3b8393 | 2018-06-12 10:43:09 -0600 | [diff] [blame] | 169 | help |
| 170 | This option determines the size of the stack within the SMM handler |
| 171 | modules. |
| 172 | |
Marshall Dawson | 46fc6847 | 2018-10-25 13:01:55 -0600 | [diff] [blame] | 173 | config SMM_STUB_STACK_SIZE |
| 174 | hex |
| 175 | default 0x400 |
Marshall Dawson | 46fc6847 | 2018-10-25 13:01:55 -0600 | [diff] [blame] | 176 | help |
| 177 | This option determines the size of the stack within the SMM handler |
| 178 | modules. |
| 179 | |
Kyösti Mälkki | 8abf66e | 2019-07-08 09:56:00 +0300 | [diff] [blame] | 180 | endif |
| 181 | |
Patrick Georgi | ce2564a | 2015-09-05 20:21:24 +0200 | [diff] [blame] | 182 | config SMM_LAPIC_REMAP_MITIGATION |
| 183 | bool |
Arthur Heymans | 912a262 | 2019-11-28 09:48:26 +0100 | [diff] [blame] | 184 | default y if NORTHBRIDGE_INTEL_I945 || NORTHBRIDGE_INTEL_GM45 \ |
| 185 | || NORTHBRIDGE_INTEL_X4X || NORTHBRIDGE_INTEL_PINEVIEW \ |
Arthur Heymans | eb76a45 | 2022-11-01 23:26:07 +0100 | [diff] [blame] | 186 | || NORTHBRIDGE_INTEL_IRONLAKE |
Patrick Georgi | ce2564a | 2015-09-05 20:21:24 +0200 | [diff] [blame] | 187 | default n |
| 188 | |
Aaron Durbin | 57686f8 | 2013-03-20 15:50:59 -0500 | [diff] [blame] | 189 | config X86_AMD_FIXED_MTRRS |
| 190 | bool |
| 191 | default n |
| 192 | help |
| 193 | This option informs the MTRR code to use the RdMem and WrMem fields |
| 194 | in the fixed MTRR MSRs. |
Aaron Durbin | e0785c0 | 2013-10-21 12:15:29 -0500 | [diff] [blame] | 195 | |
Subrata Banik | 9f91ced | 2021-07-28 15:38:32 +0530 | [diff] [blame] | 196 | config X86_INIT_NEED_1_SIPI |
Marshall Dawson | 98f43a1 | 2019-08-05 16:18:56 -0600 | [diff] [blame] | 197 | bool |
| 198 | default n |
| 199 | help |
| 200 | This option limits the number of SIPI signals sent during during the |
| 201 | common AP setup. Intel documentation specifies an INIT SIPI SIPI |
Subrata Banik | 9f91ced | 2021-07-28 15:38:32 +0530 | [diff] [blame] | 202 | sequence, however this doesn't work on some AMD and Intel platforms. |
| 203 | These newer AMD and Intel platforms don't need the 10ms wait between |
| 204 | INIT and SIPI, so skip that too to save some time. |
Marshall Dawson | 98f43a1 | 2019-08-05 16:18:56 -0600 | [diff] [blame] | 205 | |
Lee Leahy | ae738ac | 2016-07-24 08:03:37 -0700 | [diff] [blame] | 206 | config SOC_SETS_MSRS |
| 207 | bool |
| 208 | default n |
| 209 | help |
| 210 | The SoC requires different access methods for reading and writing |
| 211 | the MSRs. Use SoC specific routines to handle the MSR access. |
Tim Wawrzynczak | 6fcc46d | 2021-04-19 13:47:36 -0600 | [diff] [blame] | 212 | |
| 213 | config RESERVE_MTRRS_FOR_OS |
| 214 | bool |
| 215 | default n |
| 216 | help |
| 217 | This option allows a platform to reserve 2 MTRRs for the OS usage. |
| 218 | The Intel SDM documents that the the first 6 MTRRs are intended for |
| 219 | the system BIOS and the last 2 are to be reserved for OS usage. |
| 220 | However, modern OSes use PAT to control cacheability instead of |
| 221 | using MTRRs. |
Raul E Rangel | b2346a5 | 2021-09-22 14:56:51 -0600 | [diff] [blame] | 222 | |
| 223 | config CPU_INFO_V2 |
| 224 | bool |
| 225 | depends on PARALLEL_MP |
| 226 | help |
| 227 | Enables the new method of locating struct cpu_info. This new method |
| 228 | uses the %gs segment to locate the cpu_info pointer. The old method |
| 229 | relied on the stack being CONFIG_STACK_SIZE aligned. |
Arthur Heymans | 67f29e8 | 2022-04-17 10:37:13 +0200 | [diff] [blame] | 230 | |
| 231 | endif # ARCH_X86 |