Furquan Shaikh | da01d94 | 2014-03-19 14:31:23 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Deepa Dinamani | 2c04117 | 2014-05-15 17:14:12 -0700 | [diff] [blame] | 4 | * Copyright 2014 Google Inc. |
Furquan Shaikh | da01d94 | 2014-03-19 14:31:23 -0700 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
Deepa Dinamani | 2c04117 | 2014-05-15 17:14:12 -0700 | [diff] [blame] | 20 | #include <arch/cache.h> |
Vadim Bendebury | 1de971d | 2014-08-07 15:20:21 -0700 | [diff] [blame] | 21 | #include <boardid.h> |
Furquan Shaikh | da01d94 | 2014-03-19 14:31:23 -0700 | [diff] [blame] | 22 | #include <boot/coreboot_tables.h> |
Vadim Bendebury | c6d3040 | 2014-08-01 17:36:45 -0700 | [diff] [blame] | 23 | #include <delay.h> |
Vadim Bendebury | 1de971d | 2014-08-07 15:20:21 -0700 | [diff] [blame] | 24 | #include <device/device.h> |
Julius Werner | eaa9c45 | 2014-09-24 15:40:49 -0700 | [diff] [blame] | 25 | #include <gpio.h> |
Julius Werner | 73d1ed6 | 2014-10-20 13:20:49 -0700 | [diff] [blame] | 26 | #include <soc/clock.h> |
Vikas Das | 08f249e | 2014-09-22 17:49:56 -0700 | [diff] [blame] | 27 | #include <soc/soc_services.h> |
Julius Werner | 73d1ed6 | 2014-10-20 13:20:49 -0700 | [diff] [blame] | 28 | #include <soc/usb.h> |
Julius Werner | ec5e5e0 | 2014-08-20 15:29:56 -0700 | [diff] [blame] | 29 | #include <symbols.h> |
Vadim Bendebury | c6d3040 | 2014-08-01 17:36:45 -0700 | [diff] [blame] | 30 | |
Vadim Bendebury | 103a07f | 2014-10-23 16:03:29 -0700 | [diff] [blame] | 31 | #include <vendorcode/google/chromeos/chromeos.h> |
| 32 | |
Deepa Dinamani | 2c04117 | 2014-05-15 17:14:12 -0700 | [diff] [blame] | 33 | /* convenient shorthand (in MB) */ |
Julius Werner | ec5e5e0 | 2014-08-20 15:29:56 -0700 | [diff] [blame] | 34 | #define DRAM_START ((uintptr_t)_dram / MiB) |
Deepa Dinamani | 2c04117 | 2014-05-15 17:14:12 -0700 | [diff] [blame] | 35 | #define DRAM_SIZE (CONFIG_DRAM_SIZE_MB) |
| 36 | #define DRAM_END (DRAM_START + DRAM_SIZE) |
| 37 | |
| 38 | /* DMA memory for drivers */ |
Julius Werner | ec5e5e0 | 2014-08-20 15:29:56 -0700 | [diff] [blame] | 39 | #define DMA_START ((uintptr_t)_dma_coherent / MiB) |
| 40 | #define DMA_SIZE (_dma_coherent_size / MiB) |
Julius Werner | 028cba9 | 2014-05-30 18:01:44 -0700 | [diff] [blame] | 41 | |
Vadim Bendebury | f6ad832 | 2014-06-24 07:26:03 -0700 | [diff] [blame] | 42 | #define USB_ENABLE_GPIO 51 |
| 43 | |
Julius Werner | 028cba9 | 2014-05-30 18:01:44 -0700 | [diff] [blame] | 44 | static void setup_usb(void) |
| 45 | { |
Vadim Bendebury | f752d01 | 2014-07-10 15:24:18 -0700 | [diff] [blame] | 46 | #if !CONFIG_BOARD_VARIANT_AP148 |
Vadim Bendebury | f6ad832 | 2014-06-24 07:26:03 -0700 | [diff] [blame] | 47 | gpio_tlmm_config_set(USB_ENABLE_GPIO, FUNC_SEL_GPIO, |
| 48 | GPIO_PULL_UP, GPIO_10MA, GPIO_ENABLE); |
Julius Werner | eaa9c45 | 2014-09-24 15:40:49 -0700 | [diff] [blame] | 49 | gpio_set(USB_ENABLE_GPIO, 1); |
Vadim Bendebury | f752d01 | 2014-07-10 15:24:18 -0700 | [diff] [blame] | 50 | #endif |
Julius Werner | 028cba9 | 2014-05-30 18:01:44 -0700 | [diff] [blame] | 51 | usb_clock_config(); |
| 52 | |
| 53 | setup_usb_host1(); |
Julius Werner | 028cba9 | 2014-05-30 18:01:44 -0700 | [diff] [blame] | 54 | } |
Deepa Dinamani | 2c04117 | 2014-05-15 17:14:12 -0700 | [diff] [blame] | 55 | |
| 56 | static void setup_mmu(void) |
| 57 | { |
| 58 | dcache_mmu_disable(); |
| 59 | |
| 60 | /* Map Device memory. */ |
| 61 | mmu_config_range(0, DRAM_START, DCACHE_OFF); |
| 62 | /* Disable Page 0 for trapping NULL pointer references. */ |
| 63 | mmu_disable_range(0, 1); |
| 64 | /* Map DRAM memory */ |
| 65 | mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); |
| 66 | /* Map DMA memory */ |
Julius Werner | 028cba9 | 2014-05-30 18:01:44 -0700 | [diff] [blame] | 67 | mmu_config_range(DMA_START, DMA_SIZE, DCACHE_OFF); |
Deepa Dinamani | 2c04117 | 2014-05-15 17:14:12 -0700 | [diff] [blame] | 68 | |
| 69 | mmu_disable_range(DRAM_END, 4096 - DRAM_END); |
| 70 | |
| 71 | mmu_init(); |
| 72 | |
| 73 | dcache_mmu_enable(); |
| 74 | } |
Furquan Shaikh | da01d94 | 2014-03-19 14:31:23 -0700 | [diff] [blame] | 75 | |
Vadim Bendebury | 1de971d | 2014-08-07 15:20:21 -0700 | [diff] [blame] | 76 | #define TPM_RESET_GPIO 22 |
| 77 | static void setup_tpm(void) |
| 78 | { |
Dan Ehrenberg | 644afa7 | 2014-10-24 13:22:05 -0700 | [diff] [blame] | 79 | if (board_id() != BOARD_ID_PROTO_0) |
Vadim Bendebury | 1de971d | 2014-08-07 15:20:21 -0700 | [diff] [blame] | 80 | return; /* Only proto0 have TPM reset connected to GPIO22 */ |
| 81 | |
| 82 | gpio_tlmm_config_set(TPM_RESET_GPIO, FUNC_SEL_GPIO, GPIO_PULL_UP, |
| 83 | GPIO_4MA, GPIO_ENABLE); |
| 84 | /* |
| 85 | * Generate a reset pulse. The spec calls for 80 us minimum, let's |
| 86 | * make it twice as long. If the output was driven low originally, the |
| 87 | * reset pulse will be even longer. |
| 88 | */ |
Julius Werner | eaa9c45 | 2014-09-24 15:40:49 -0700 | [diff] [blame] | 89 | gpio_set(TPM_RESET_GPIO, 0); |
Vadim Bendebury | 1de971d | 2014-08-07 15:20:21 -0700 | [diff] [blame] | 90 | udelay(160); |
Julius Werner | eaa9c45 | 2014-09-24 15:40:49 -0700 | [diff] [blame] | 91 | gpio_set(TPM_RESET_GPIO, 1); |
Vadim Bendebury | 1de971d | 2014-08-07 15:20:21 -0700 | [diff] [blame] | 92 | } |
| 93 | |
Vadim Bendebury | c7bbc04 | 2014-09-08 14:34:09 -0700 | [diff] [blame] | 94 | #define SW_RESET_GPIO 26 |
Vadim Bendebury | a45d5d3 | 2014-10-22 12:14:29 -0700 | [diff] [blame] | 95 | static void assert_sw_reset(void) |
Vadim Bendebury | c7bbc04 | 2014-09-08 14:34:09 -0700 | [diff] [blame] | 96 | { |
Dan Ehrenberg | 644afa7 | 2014-10-24 13:22:05 -0700 | [diff] [blame] | 97 | if (board_id() == BOARD_ID_PROTO_0) |
Vadim Bendebury | c7bbc04 | 2014-09-08 14:34:09 -0700 | [diff] [blame] | 98 | return; |
| 99 | |
Vadim Bendebury | f32ef13 | 2014-09-09 20:41:33 -0700 | [diff] [blame] | 100 | /* |
Vadim Bendebury | a45d5d3 | 2014-10-22 12:14:29 -0700 | [diff] [blame] | 101 | * only proto0.2 and later care about this. We want to keep the |
| 102 | * ethernet switch in reset, otherwise it comes up in default |
| 103 | * (bridging) mode. |
Vadim Bendebury | f32ef13 | 2014-09-09 20:41:33 -0700 | [diff] [blame] | 104 | */ |
Vadim Bendebury | c7bbc04 | 2014-09-08 14:34:09 -0700 | [diff] [blame] | 105 | gpio_tlmm_config_set(SW_RESET_GPIO, FUNC_SEL_GPIO, |
| 106 | GPIO_PULL_UP, GPIO_4MA, GPIO_ENABLE); |
| 107 | |
Vadim Bendebury | a45d5d3 | 2014-10-22 12:14:29 -0700 | [diff] [blame] | 108 | gpio_set(SW_RESET_GPIO, 1); |
Vadim Bendebury | c7bbc04 | 2014-09-08 14:34:09 -0700 | [diff] [blame] | 109 | } |
| 110 | |
Furquan Shaikh | da01d94 | 2014-03-19 14:31:23 -0700 | [diff] [blame] | 111 | static void mainboard_init(device_t dev) |
| 112 | { |
Vikas Das | 08f249e | 2014-09-22 17:49:56 -0700 | [diff] [blame] | 113 | start_tzbsp(); |
Vadim Bendebury | 6114c99 | 2014-12-16 14:34:28 -0800 | [diff] [blame^] | 114 | start_rpm(); |
Deepa Dinamani | 2c04117 | 2014-05-15 17:14:12 -0700 | [diff] [blame] | 115 | setup_mmu(); |
Julius Werner | 028cba9 | 2014-05-30 18:01:44 -0700 | [diff] [blame] | 116 | setup_usb(); |
Vadim Bendebury | a45d5d3 | 2014-10-22 12:14:29 -0700 | [diff] [blame] | 117 | assert_sw_reset(); |
Vadim Bendebury | 1de971d | 2014-08-07 15:20:21 -0700 | [diff] [blame] | 118 | setup_tpm(); |
Dan Ehrenberg | cb3b0c5a | 2014-10-23 17:46:39 -0700 | [diff] [blame] | 119 | /* Functionally a 0-cost no-op if NAND is not present */ |
| 120 | board_nand_init(); |
Vadim Bendebury | 103a07f | 2014-10-23 16:03:29 -0700 | [diff] [blame] | 121 | |
| 122 | #if IS_ENABLED(CONFIG_CHROMEOS) |
| 123 | /* Copy WIFI calibration data into CBMEM. */ |
| 124 | cbmem_add_vpd_calibration_data(); |
| 125 | #endif |
Furquan Shaikh | da01d94 | 2014-03-19 14:31:23 -0700 | [diff] [blame] | 126 | } |
| 127 | |
| 128 | static void mainboard_enable(device_t dev) |
| 129 | { |
| 130 | dev->ops->init = &mainboard_init; |
| 131 | } |
| 132 | |
| 133 | struct chip_operations mainboard_ops = { |
| 134 | .name = "storm", |
| 135 | .enable_dev = mainboard_enable, |
| 136 | }; |
Julius Werner | 028cba9 | 2014-05-30 18:01:44 -0700 | [diff] [blame] | 137 | |
| 138 | void lb_board(struct lb_header *header) |
| 139 | { |
| 140 | struct lb_range *dma; |
| 141 | |
| 142 | dma = (struct lb_range *)lb_new_record(header); |
| 143 | dma->tag = LB_TAB_DMA; |
| 144 | dma->size = sizeof(*dma); |
Julius Werner | ec5e5e0 | 2014-08-20 15:29:56 -0700 | [diff] [blame] | 145 | dma->range_start = (uintptr_t)_dma_coherent; |
| 146 | dma->range_size = _dma_coherent_size; |
Vadim Bendebury | e9e0eec | 2014-10-16 13:26:59 -0700 | [diff] [blame] | 147 | |
| 148 | #if IS_ENABLED(CONFIG_CHROMEOS) |
| 149 | /* Retrieve the switch interface MAC addressses. */ |
| 150 | lb_table_add_macs_from_vpd(header); |
| 151 | #endif |
Julius Werner | 028cba9 | 2014-05-30 18:01:44 -0700 | [diff] [blame] | 152 | } |