Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 2 | |
Arthur Heymans | 026863b | 2019-11-21 08:24:02 +0100 | [diff] [blame] | 3 | #define __SIMPLE_DEVICE__ |
| 4 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 5 | /* This file is derived from the flashrom project. */ |
Elyes HAOUAS | 361a935 | 2019-12-18 21:26:33 +0100 | [diff] [blame] | 6 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 7 | #include <stdint.h> |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 8 | #include <string.h> |
David Hendricks | f2612a1 | 2014-04-13 16:27:02 -0700 | [diff] [blame] | 9 | #include <bootstate.h> |
Furquan Shaikh | de705fa | 2017-04-19 19:27:28 -0700 | [diff] [blame] | 10 | #include <commonlib/helpers.h> |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 11 | #include <delay.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 12 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 13 | #include <device/pci_ops.h> |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 14 | #include <console/console.h> |
Kyösti Mälkki | 7ba1440 | 2019-02-07 12:44:00 +0200 | [diff] [blame] | 15 | #include <device/device.h> |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 16 | #include <device/pci.h> |
| 17 | #include <spi_flash.h> |
Zheng Bao | 600784e | 2013-02-07 17:30:23 +0800 | [diff] [blame] | 18 | #include <spi-generic.h> |
Aaron Durbin | 4ed8e9c | 2019-12-27 14:30:51 -0700 | [diff] [blame] | 19 | #include <timer.h> |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 20 | |
Arthur Heymans | 92185e3 | 2019-05-28 13:06:34 +0200 | [diff] [blame] | 21 | #include "spi.h" |
| 22 | |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 23 | #define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */ |
| 24 | #define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF) |
| 25 | #define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ |
| 26 | #define HSFC_FDBC (0x3f << HSFC_FDBC_OFF) |
| 27 | |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 28 | static int spi_is_multichip(void); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 29 | |
Arthur Heymans | a9c1a5f | 2019-06-15 18:21:58 +0200 | [diff] [blame] | 30 | struct ich7_spi_regs { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 31 | uint16_t spis; |
| 32 | uint16_t spic; |
| 33 | uint32_t spia; |
| 34 | uint64_t spid[8]; |
| 35 | uint64_t _pad; |
| 36 | uint32_t bbar; |
| 37 | uint16_t preop; |
| 38 | uint16_t optype; |
| 39 | uint8_t opmenu[8]; |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 40 | uint32_t pbr[3]; |
Arthur Heymans | a9c1a5f | 2019-06-15 18:21:58 +0200 | [diff] [blame] | 41 | } __packed; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 42 | |
Arthur Heymans | a9c1a5f | 2019-06-15 18:21:58 +0200 | [diff] [blame] | 43 | struct ich9_spi_regs { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 44 | uint32_t bfpr; |
| 45 | uint16_t hsfs; |
| 46 | uint16_t hsfc; |
| 47 | uint32_t faddr; |
| 48 | uint32_t _reserved0; |
| 49 | uint32_t fdata[16]; |
| 50 | uint32_t frap; |
| 51 | uint32_t freg[5]; |
| 52 | uint32_t _reserved1[3]; |
| 53 | uint32_t pr[5]; |
| 54 | uint32_t _reserved2[2]; |
| 55 | uint8_t ssfs; |
| 56 | uint8_t ssfc[3]; |
| 57 | uint16_t preop; |
| 58 | uint16_t optype; |
| 59 | uint8_t opmenu[8]; |
| 60 | uint32_t bbar; |
| 61 | uint8_t _reserved3[12]; |
| 62 | uint32_t fdoc; |
| 63 | uint32_t fdod; |
| 64 | uint8_t _reserved4[8]; |
| 65 | uint32_t afc; |
| 66 | uint32_t lvscc; |
| 67 | uint32_t uvscc; |
| 68 | uint8_t _reserved5[4]; |
| 69 | uint32_t fpb; |
| 70 | uint8_t _reserved6[28]; |
| 71 | uint32_t srdl; |
| 72 | uint32_t srdc; |
| 73 | uint32_t srd; |
Arthur Heymans | a9c1a5f | 2019-06-15 18:21:58 +0200 | [diff] [blame] | 74 | } __packed; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 75 | |
Arthur Heymans | a9c1a5f | 2019-06-15 18:21:58 +0200 | [diff] [blame] | 76 | struct ich_spi_controller { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 77 | int locked; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 78 | uint32_t flmap0; |
Stefan Tauner | 327205d | 2018-08-26 13:53:16 +0200 | [diff] [blame] | 79 | uint32_t flcomp; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 80 | uint32_t hsfs; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 81 | |
Arthur Heymans | 21c5d43 | 2019-06-15 18:23:29 +0200 | [diff] [blame] | 82 | union { |
| 83 | struct ich9_spi_regs *ich9_spi; |
| 84 | struct ich7_spi_regs *ich7_spi; |
| 85 | }; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 86 | uint8_t *opmenu; |
| 87 | int menubytes; |
| 88 | uint16_t *preop; |
| 89 | uint16_t *optype; |
| 90 | uint32_t *addr; |
| 91 | uint8_t *data; |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 92 | unsigned int databytes; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 93 | uint8_t *status; |
| 94 | uint16_t *control; |
| 95 | uint32_t *bbar; |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 96 | uint32_t *fpr; |
| 97 | uint8_t fpr_max; |
Arthur Heymans | a9c1a5f | 2019-06-15 18:21:58 +0200 | [diff] [blame] | 98 | }; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 99 | |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 100 | static struct ich_spi_controller cntlr; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 101 | |
| 102 | enum { |
| 103 | SPIS_SCIP = 0x0001, |
| 104 | SPIS_GRANT = 0x0002, |
| 105 | SPIS_CDS = 0x0004, |
| 106 | SPIS_FCERR = 0x0008, |
| 107 | SSFS_AEL = 0x0010, |
| 108 | SPIS_LOCK = 0x8000, |
| 109 | SPIS_RESERVED_MASK = 0x7ff0, |
| 110 | SSFS_RESERVED_MASK = 0x7fe2 |
| 111 | }; |
| 112 | |
| 113 | enum { |
| 114 | SPIC_SCGO = 0x000002, |
| 115 | SPIC_ACS = 0x000004, |
| 116 | SPIC_SPOP = 0x000008, |
| 117 | SPIC_DBC = 0x003f00, |
| 118 | SPIC_DS = 0x004000, |
| 119 | SPIC_SME = 0x008000, |
| 120 | SSFC_SCF_MASK = 0x070000, |
| 121 | SSFC_RESERVED = 0xf80000 |
| 122 | }; |
| 123 | |
| 124 | enum { |
| 125 | HSFS_FDONE = 0x0001, |
| 126 | HSFS_FCERR = 0x0002, |
| 127 | HSFS_AEL = 0x0004, |
| 128 | HSFS_BERASE_MASK = 0x0018, |
| 129 | HSFS_BERASE_SHIFT = 3, |
| 130 | HSFS_SCIP = 0x0020, |
| 131 | HSFS_FDOPSS = 0x2000, |
| 132 | HSFS_FDV = 0x4000, |
| 133 | HSFS_FLOCKDN = 0x8000 |
| 134 | }; |
| 135 | |
| 136 | enum { |
| 137 | HSFC_FGO = 0x0001, |
| 138 | HSFC_FCYCLE_MASK = 0x0006, |
| 139 | HSFC_FCYCLE_SHIFT = 1, |
| 140 | HSFC_FDBC_MASK = 0x3f00, |
| 141 | HSFC_FDBC_SHIFT = 8, |
| 142 | HSFC_FSMIE = 0x8000 |
| 143 | }; |
| 144 | |
| 145 | enum { |
| 146 | SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, |
| 147 | SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, |
| 148 | SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, |
| 149 | SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 |
| 150 | }; |
| 151 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 152 | #if CONFIG(DEBUG_SPI_FLASH) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 153 | |
| 154 | static u8 readb_(const void *addr) |
| 155 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 156 | u8 v = read8(addr); |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 157 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 158 | printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 159 | v, ((unsigned int) addr & 0xffff) - 0xf020); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 160 | return v; |
| 161 | } |
| 162 | |
| 163 | static u16 readw_(const void *addr) |
| 164 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 165 | u16 v = read16(addr); |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 166 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 167 | printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 168 | v, ((unsigned int) addr & 0xffff) - 0xf020); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 169 | return v; |
| 170 | } |
| 171 | |
| 172 | static u32 readl_(const void *addr) |
| 173 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 174 | u32 v = read32(addr); |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 175 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 176 | printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 177 | v, ((unsigned int) addr & 0xffff) - 0xf020); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 178 | return v; |
| 179 | } |
| 180 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 181 | static void writeb_(u8 b, void *addr) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 182 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 183 | write8(addr, b); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 184 | printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 185 | b, ((unsigned int) addr & 0xffff) - 0xf020); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 186 | } |
| 187 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 188 | static void writew_(u16 b, void *addr) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 189 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 190 | write16(addr, b); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 191 | printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 192 | b, ((unsigned int) addr & 0xffff) - 0xf020); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 193 | } |
| 194 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 195 | static void writel_(u32 b, void *addr) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 196 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 197 | write32(addr, b); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 198 | printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 199 | b, ((unsigned int) addr & 0xffff) - 0xf020); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 200 | } |
| 201 | |
| 202 | #else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ |
| 203 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 204 | #define readb_(a) read8(a) |
| 205 | #define readw_(a) read16(a) |
| 206 | #define readl_(a) read32(a) |
| 207 | #define writeb_(val, addr) write8(addr, val) |
| 208 | #define writew_(val, addr) write16(addr, val) |
| 209 | #define writel_(val, addr) write32(addr, val) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 210 | |
| 211 | #endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */ |
| 212 | |
| 213 | static void write_reg(const void *value, void *dest, uint32_t size) |
| 214 | { |
| 215 | const uint8_t *bvalue = value; |
| 216 | uint8_t *bdest = dest; |
| 217 | |
| 218 | while (size >= 4) { |
| 219 | writel_(*(const uint32_t *)bvalue, bdest); |
| 220 | bdest += 4; bvalue += 4; size -= 4; |
| 221 | } |
| 222 | while (size) { |
| 223 | writeb_(*bvalue, bdest); |
| 224 | bdest++; bvalue++; size--; |
| 225 | } |
| 226 | } |
| 227 | |
| 228 | static void read_reg(const void *src, void *value, uint32_t size) |
| 229 | { |
| 230 | const uint8_t *bsrc = src; |
| 231 | uint8_t *bvalue = value; |
| 232 | |
| 233 | while (size >= 4) { |
| 234 | *(uint32_t *)bvalue = readl_(bsrc); |
| 235 | bsrc += 4; bvalue += 4; size -= 4; |
| 236 | } |
| 237 | while (size) { |
| 238 | *bvalue = readb_(bsrc); |
| 239 | bsrc++; bvalue++; size--; |
| 240 | } |
| 241 | } |
| 242 | |
| 243 | static void ich_set_bbar(uint32_t minaddr) |
| 244 | { |
| 245 | const uint32_t bbar_mask = 0x00ffff00; |
| 246 | uint32_t ichspi_bbar; |
| 247 | |
| 248 | minaddr &= bbar_mask; |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 249 | ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 250 | ichspi_bbar |= minaddr; |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 251 | writel_(ichspi_bbar, cntlr.bbar); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 252 | } |
| 253 | |
Jacob Garber | 9172b69 | 2019-06-26 16:18:16 -0600 | [diff] [blame] | 254 | #if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) |
| 255 | #define MENU_BYTES member_size(struct ich7_spi_regs, opmenu) |
| 256 | #else |
| 257 | #define MENU_BYTES member_size(struct ich9_spi_regs, opmenu) |
| 258 | #endif |
| 259 | |
Arthur Heymans | 47a6603 | 2019-10-25 23:43:14 +0200 | [diff] [blame] | 260 | #define RCBA 0xf0 |
| 261 | #define SBASE 0x54 |
| 262 | |
Arthur Heymans | 47a6603 | 2019-10-25 23:43:14 +0200 | [diff] [blame] | 263 | static void *get_spi_bar(pci_devfn_t dev) |
Arthur Heymans | 47a6603 | 2019-10-25 23:43:14 +0200 | [diff] [blame] | 264 | { |
| 265 | uintptr_t rcba; /* Root Complex Register Block */ |
| 266 | uintptr_t sbase; |
| 267 | |
| 268 | if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) { |
| 269 | rcba = pci_read_config32(dev, RCBA); |
| 270 | return (void *)((rcba & 0xffffc000) + 0x3020); |
| 271 | } |
| 272 | if (CONFIG(SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT)) { |
| 273 | sbase = pci_read_config32(dev, SBASE); |
| 274 | sbase &= ~0x1ff; |
| 275 | return (void *)sbase; |
| 276 | } |
| 277 | if (CONFIG(SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9)) { |
| 278 | rcba = pci_read_config32(dev, RCBA); |
| 279 | return (void *)((rcba & 0xffffc000) + 0x3800); |
| 280 | } |
| 281 | } |
| 282 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 283 | void spi_init(void) |
| 284 | { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 285 | uint8_t bios_cntl; |
Arthur Heymans | a9c1a5f | 2019-06-15 18:21:58 +0200 | [diff] [blame] | 286 | struct ich9_spi_regs *ich9_spi; |
| 287 | struct ich7_spi_regs *ich7_spi; |
Vladimir Serbinenko | 42c4a9d | 2014-02-16 17:13:19 +0100 | [diff] [blame] | 288 | uint16_t hsfs; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 289 | |
Elyes HAOUAS | 68c851b | 2018-06-12 22:06:09 +0200 | [diff] [blame] | 290 | pci_devfn_t dev = PCI_DEV(0, 31, 0); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 291 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 292 | if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) { |
Arthur Heymans | 47a6603 | 2019-10-25 23:43:14 +0200 | [diff] [blame] | 293 | ich7_spi = get_spi_bar(dev); |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 294 | cntlr.ich7_spi = ich7_spi; |
| 295 | cntlr.opmenu = ich7_spi->opmenu; |
| 296 | cntlr.menubytes = sizeof(ich7_spi->opmenu); |
| 297 | cntlr.optype = &ich7_spi->optype; |
| 298 | cntlr.addr = &ich7_spi->spia; |
| 299 | cntlr.data = (uint8_t *)ich7_spi->spid; |
| 300 | cntlr.databytes = sizeof(ich7_spi->spid); |
| 301 | cntlr.status = (uint8_t *)&ich7_spi->spis; |
| 302 | cntlr.control = &ich7_spi->spic; |
| 303 | cntlr.bbar = &ich7_spi->bbar; |
| 304 | cntlr.preop = &ich7_spi->preop; |
| 305 | cntlr.fpr = &ich7_spi->pbr[0]; |
| 306 | cntlr.fpr_max = 3; |
Arthur Heymans | c88e370 | 2017-08-20 20:50:17 +0200 | [diff] [blame] | 307 | } else { |
Arthur Heymans | 47a6603 | 2019-10-25 23:43:14 +0200 | [diff] [blame] | 308 | ich9_spi = get_spi_bar(dev); |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 309 | cntlr.ich9_spi = ich9_spi; |
Arthur Heymans | c88e370 | 2017-08-20 20:50:17 +0200 | [diff] [blame] | 310 | hsfs = readw_(&ich9_spi->hsfs); |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 311 | cntlr.hsfs = hsfs; |
| 312 | cntlr.opmenu = ich9_spi->opmenu; |
| 313 | cntlr.menubytes = sizeof(ich9_spi->opmenu); |
| 314 | cntlr.optype = &ich9_spi->optype; |
| 315 | cntlr.addr = &ich9_spi->faddr; |
| 316 | cntlr.data = (uint8_t *)ich9_spi->fdata; |
| 317 | cntlr.databytes = sizeof(ich9_spi->fdata); |
| 318 | cntlr.status = &ich9_spi->ssfs; |
| 319 | cntlr.control = (uint16_t *)ich9_spi->ssfc; |
| 320 | cntlr.bbar = &ich9_spi->bbar; |
| 321 | cntlr.preop = &ich9_spi->preop; |
| 322 | cntlr.fpr = &ich9_spi->pr[0]; |
| 323 | cntlr.fpr_max = 5; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 324 | |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 325 | if (cntlr.hsfs & HSFS_FDV) { |
Patrick Georgi | c88828d | 2018-11-26 10:42:59 +0100 | [diff] [blame] | 326 | writel_(4, &ich9_spi->fdoc); |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 327 | cntlr.flmap0 = readl_(&ich9_spi->fdod); |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 328 | writel_(0x1000, &ich9_spi->fdoc); |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 329 | cntlr.flcomp = readl_(&ich9_spi->fdod); |
Arthur Heymans | c88e370 | 2017-08-20 20:50:17 +0200 | [diff] [blame] | 330 | } |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 331 | } |
| 332 | |
| 333 | ich_set_bbar(0); |
| 334 | |
Arthur Heymans | 47a6603 | 2019-10-25 23:43:14 +0200 | [diff] [blame] | 335 | if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX) || CONFIG(SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9)) { |
| 336 | /* Disable the BIOS write protect so write commands are allowed. */ |
| 337 | bios_cntl = pci_read_config8(dev, 0xdc); |
| 338 | /* Deassert SMM BIOS Write Protect Disable. */ |
| 339 | bios_cntl &= ~(1 << 5); |
| 340 | pci_write_config8(dev, 0xdc, bios_cntl | 0x1); |
| 341 | } |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 342 | } |
Aaron Durbin | 4d3de7e | 2015-09-02 17:34:04 -0500 | [diff] [blame] | 343 | |
Arthur Heymans | 816aaba | 2019-06-11 11:10:25 +0200 | [diff] [blame] | 344 | static int spi_locked(void) |
| 345 | { |
Arthur Heymans | 816aaba | 2019-06-11 11:10:25 +0200 | [diff] [blame] | 346 | if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) { |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 347 | return !!(readw_(&cntlr.ich7_spi->spis) & HSFS_FLOCKDN); |
Arthur Heymans | 816aaba | 2019-06-11 11:10:25 +0200 | [diff] [blame] | 348 | } else { |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 349 | return !!(readw_(&cntlr.ich9_spi->hsfs) & HSFS_FLOCKDN); |
Arthur Heymans | 816aaba | 2019-06-11 11:10:25 +0200 | [diff] [blame] | 350 | } |
| 351 | } |
| 352 | |
David Hendricks | f2612a1 | 2014-04-13 16:27:02 -0700 | [diff] [blame] | 353 | static void spi_init_cb(void *unused) |
| 354 | { |
| 355 | spi_init(); |
| 356 | } |
| 357 | |
Aaron Durbin | 9ef9d85 | 2015-03-16 17:30:09 -0500 | [diff] [blame] | 358 | BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 359 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 360 | typedef struct spi_transaction { |
| 361 | const uint8_t *out; |
| 362 | uint32_t bytesout; |
| 363 | uint8_t *in; |
| 364 | uint32_t bytesin; |
| 365 | uint8_t type; |
| 366 | uint8_t opcode; |
| 367 | uint32_t offset; |
| 368 | } spi_transaction; |
| 369 | |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 370 | static inline void spi_use_out(spi_transaction *trans, unsigned int bytes) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 371 | { |
| 372 | trans->out += bytes; |
| 373 | trans->bytesout -= bytes; |
| 374 | } |
| 375 | |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 376 | static inline void spi_use_in(spi_transaction *trans, unsigned int bytes) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 377 | { |
| 378 | trans->in += bytes; |
| 379 | trans->bytesin -= bytes; |
| 380 | } |
| 381 | |
| 382 | static void spi_setup_type(spi_transaction *trans) |
| 383 | { |
| 384 | trans->type = 0xFF; |
| 385 | |
| 386 | /* Try to guess spi type from read/write sizes. */ |
| 387 | if (trans->bytesin == 0) { |
| 388 | if (trans->bytesout > 4) |
| 389 | /* |
| 390 | * If bytesin = 0 and bytesout > 4, we presume this is |
| 391 | * a write data operation, which is accompanied by an |
| 392 | * address. |
| 393 | */ |
| 394 | trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; |
| 395 | else |
| 396 | trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; |
| 397 | return; |
| 398 | } |
| 399 | |
| 400 | if (trans->bytesout == 1) { /* and bytesin is > 0 */ |
| 401 | trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; |
| 402 | return; |
| 403 | } |
| 404 | |
| 405 | if (trans->bytesout == 4) { /* and bytesin is > 0 */ |
| 406 | trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; |
| 407 | } |
Duncan Laurie | 23b0053 | 2012-10-10 14:21:23 -0700 | [diff] [blame] | 408 | |
| 409 | /* Fast read command is called with 5 bytes instead of 4 */ |
| 410 | if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { |
| 411 | trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; |
| 412 | --trans->bytesout; |
| 413 | } |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 414 | } |
| 415 | |
| 416 | static int spi_setup_opcode(spi_transaction *trans) |
| 417 | { |
| 418 | uint16_t optypes; |
Jacob Garber | 9172b69 | 2019-06-26 16:18:16 -0600 | [diff] [blame] | 419 | uint8_t opmenu[MENU_BYTES]; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 420 | |
| 421 | trans->opcode = trans->out[0]; |
| 422 | spi_use_out(trans, 1); |
Arthur Heymans | 816aaba | 2019-06-11 11:10:25 +0200 | [diff] [blame] | 423 | if (!spi_locked()) { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 424 | /* The lock is off, so just use index 0. */ |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 425 | writeb_(trans->opcode, cntlr.opmenu); |
| 426 | optypes = readw_(cntlr.optype); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 427 | optypes = (optypes & 0xfffc) | (trans->type & 0x3); |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 428 | writew_(optypes, cntlr.optype); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 429 | return 0; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 430 | } |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 431 | |
| 432 | /* The lock is on. See if what we need is on the menu. */ |
| 433 | uint8_t optype; |
| 434 | uint16_t opcode_index; |
| 435 | |
| 436 | /* Write Enable is handled as atomic prefix */ |
| 437 | if (trans->opcode == SPI_OPCODE_WREN) |
| 438 | return 0; |
| 439 | |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 440 | read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); |
Jacob Garber | 9172b69 | 2019-06-26 16:18:16 -0600 | [diff] [blame] | 441 | for (opcode_index = 0; opcode_index < ARRAY_SIZE(opmenu); opcode_index++) { |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 442 | if (opmenu[opcode_index] == trans->opcode) |
| 443 | break; |
| 444 | } |
| 445 | |
Jacob Garber | 9172b69 | 2019-06-26 16:18:16 -0600 | [diff] [blame] | 446 | if (opcode_index == ARRAY_SIZE(opmenu)) { |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 447 | printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", |
| 448 | trans->opcode); |
| 449 | return -1; |
| 450 | } |
| 451 | |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 452 | optypes = readw_(cntlr.optype); |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 453 | optype = (optypes >> (opcode_index * 2)) & 0x3; |
| 454 | if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && |
| 455 | optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && |
| 456 | trans->bytesout >= 3) { |
| 457 | /* We guessed wrong earlier. Fix it up. */ |
| 458 | trans->type = optype; |
| 459 | } |
| 460 | if (optype != trans->type) { |
| 461 | printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n", |
| 462 | optype); |
| 463 | return -1; |
| 464 | } |
| 465 | return opcode_index; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 466 | } |
| 467 | |
| 468 | static int spi_setup_offset(spi_transaction *trans) |
| 469 | { |
| 470 | /* Separate the SPI address and data. */ |
| 471 | switch (trans->type) { |
| 472 | case SPI_OPCODE_TYPE_READ_NO_ADDRESS: |
| 473 | case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: |
| 474 | return 0; |
| 475 | case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: |
| 476 | case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: |
| 477 | trans->offset = ((uint32_t)trans->out[0] << 16) | |
| 478 | ((uint32_t)trans->out[1] << 8) | |
| 479 | ((uint32_t)trans->out[2] << 0); |
| 480 | spi_use_out(trans, 3); |
| 481 | return 1; |
| 482 | default: |
| 483 | printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type); |
| 484 | return -1; |
| 485 | } |
| 486 | } |
| 487 | |
| 488 | /* |
Philipp Deppenwiese | 93643e3 | 2014-10-17 16:10:32 +0200 | [diff] [blame] | 489 | * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 490 | * below is True) or 0. In case the wait was for the bit(s) to set - write |
| 491 | * those bits back, which would cause resetting them. |
| 492 | * |
| 493 | * Return the last read status value on success or -1 on failure. |
| 494 | */ |
| 495 | static int ich_status_poll(u16 bitmask, int wait_til_set) |
| 496 | { |
Philipp Deppenwiese | 93643e3 | 2014-10-17 16:10:32 +0200 | [diff] [blame] | 497 | int timeout = 600000; /* This will result in 6 seconds */ |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 498 | u16 status = 0; |
| 499 | |
| 500 | while (timeout--) { |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 501 | status = readw_(cntlr.status); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 502 | if (wait_til_set ^ ((status & bitmask) == 0)) { |
| 503 | if (wait_til_set) |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 504 | writew_((status & bitmask), cntlr.status); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 505 | return status; |
| 506 | } |
| 507 | udelay(10); |
| 508 | } |
| 509 | |
Philipp Deppenwiese | 93643e3 | 2014-10-17 16:10:32 +0200 | [diff] [blame] | 510 | printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, bitmask %x\n", |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 511 | status, bitmask); |
| 512 | return -1; |
| 513 | } |
| 514 | |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 515 | static int spi_is_multichip(void) |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 516 | { |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 517 | if (!(cntlr.hsfs & HSFS_FDV)) |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 518 | return 0; |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 519 | return !!((cntlr.flmap0 >> 8) & 3); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 520 | } |
| 521 | |
Furquan Shaikh | 94f8699 | 2016-12-01 07:12:32 -0800 | [diff] [blame] | 522 | static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, |
Furquan Shaikh | 0dba025 | 2016-11-30 04:34:22 -0800 | [diff] [blame] | 523 | size_t bytesout, void *din, size_t bytesin) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 524 | { |
| 525 | uint16_t control; |
| 526 | int16_t opcode_index; |
| 527 | int with_address; |
| 528 | int status; |
| 529 | |
| 530 | spi_transaction trans = { |
Gabe Black | 93d9f92 | 2014-03-27 21:52:43 -0700 | [diff] [blame] | 531 | dout, bytesout, |
| 532 | din, bytesin, |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 533 | 0xff, 0xff, 0 |
| 534 | }; |
| 535 | |
| 536 | /* There has to always at least be an opcode. */ |
Gabe Black | 93d9f92 | 2014-03-27 21:52:43 -0700 | [diff] [blame] | 537 | if (!bytesout || !dout) { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 538 | printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n"); |
| 539 | return -1; |
| 540 | } |
| 541 | /* Make sure if we read something we have a place to put it. */ |
Gabe Black | 93d9f92 | 2014-03-27 21:52:43 -0700 | [diff] [blame] | 542 | if (bytesin != 0 && !din) { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 543 | printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n"); |
| 544 | return -1; |
| 545 | } |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 546 | |
| 547 | if (ich_status_poll(SPIS_SCIP, 0) == -1) |
| 548 | return -1; |
| 549 | |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 550 | writew_(SPIS_CDS | SPIS_FCERR, cntlr.status); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 551 | |
| 552 | spi_setup_type(&trans); |
| 553 | if ((opcode_index = spi_setup_opcode(&trans)) < 0) |
| 554 | return -1; |
| 555 | if ((with_address = spi_setup_offset(&trans)) < 0) |
| 556 | return -1; |
| 557 | |
Duncan Laurie | 3beb6db | 2012-09-01 13:44:17 -0700 | [diff] [blame] | 558 | if (trans.opcode == SPI_OPCODE_WREN) { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 559 | /* |
| 560 | * Treat Write Enable as Atomic Pre-Op if possible |
| 561 | * in order to prevent the Management Engine from |
| 562 | * issuing a transaction between WREN and DATA. |
| 563 | */ |
Arthur Heymans | 816aaba | 2019-06-11 11:10:25 +0200 | [diff] [blame] | 564 | if (!spi_locked()) |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 565 | writew_(trans.opcode, cntlr.preop); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 566 | return 0; |
| 567 | } |
| 568 | |
| 569 | /* Preset control fields */ |
| 570 | control = SPIC_SCGO | ((opcode_index & 0x07) << 4); |
| 571 | |
| 572 | /* Issue atomic preop cycle if needed */ |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 573 | if (readw_(cntlr.preop)) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 574 | control |= SPIC_ACS; |
| 575 | |
| 576 | if (!trans.bytesout && !trans.bytesin) { |
Duncan Laurie | 3beb6db | 2012-09-01 13:44:17 -0700 | [diff] [blame] | 577 | /* SPI addresses are 24 bit only */ |
| 578 | if (with_address) |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 579 | writel_(trans.offset & 0x00FFFFFF, cntlr.addr); |
Duncan Laurie | 3beb6db | 2012-09-01 13:44:17 -0700 | [diff] [blame] | 580 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 581 | /* |
| 582 | * This is a 'no data' command (like Write Enable), its |
| 583 | * bitesout size was 1, decremented to zero while executing |
| 584 | * spi_setup_opcode() above. Tell the chip to send the |
| 585 | * command. |
| 586 | */ |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 587 | writew_(control, cntlr.control); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 588 | |
| 589 | /* wait for the result */ |
| 590 | status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); |
| 591 | if (status == -1) |
| 592 | return -1; |
| 593 | |
| 594 | if (status & SPIS_FCERR) { |
| 595 | printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n"); |
| 596 | return -1; |
| 597 | } |
| 598 | |
Werner Zeh | f13a6f9 | 2018-11-14 10:55:52 +0100 | [diff] [blame] | 599 | goto spi_xfer_exit; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 600 | } |
| 601 | |
| 602 | /* |
Paul Menzel | 9478297 | 2013-06-29 11:41:27 +0200 | [diff] [blame] | 603 | * Check if this is a write command attempting to transfer more bytes |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 604 | * than the controller can handle. Iterations for writes are not |
| 605 | * supported here because each SPI write command needs to be preceded |
| 606 | * and followed by other SPI commands, and this sequence is controlled |
| 607 | * by the SPI chip driver. |
| 608 | */ |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 609 | if (trans.bytesout > cntlr.databytes) { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 610 | printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" |
Kyösti Mälkki | 1110495 | 2014-06-29 16:17:33 +0300 | [diff] [blame] | 611 | " spi_crop_chunk()?\n"); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 612 | return -1; |
| 613 | } |
| 614 | |
| 615 | /* |
| 616 | * Read or write up to databytes bytes at a time until everything has |
| 617 | * been sent. |
| 618 | */ |
| 619 | while (trans.bytesout || trans.bytesin) { |
| 620 | uint32_t data_length; |
| 621 | |
| 622 | /* SPI addresses are 24 bit only */ |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 623 | writel_(trans.offset & 0x00FFFFFF, cntlr.addr); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 624 | |
| 625 | if (trans.bytesout) |
Elyes HAOUAS | 361a935 | 2019-12-18 21:26:33 +0100 | [diff] [blame] | 626 | data_length = MIN(trans.bytesout, cntlr.databytes); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 627 | else |
Elyes HAOUAS | 361a935 | 2019-12-18 21:26:33 +0100 | [diff] [blame] | 628 | data_length = MIN(trans.bytesin, cntlr.databytes); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 629 | |
| 630 | /* Program data into FDATA0 to N */ |
| 631 | if (trans.bytesout) { |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 632 | write_reg(trans.out, cntlr.data, data_length); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 633 | spi_use_out(&trans, data_length); |
| 634 | if (with_address) |
| 635 | trans.offset += data_length; |
| 636 | } |
| 637 | |
| 638 | /* Add proper control fields' values */ |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 639 | control &= ~((cntlr.databytes - 1) << 8); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 640 | control |= SPIC_DS; |
| 641 | control |= (data_length - 1) << 8; |
| 642 | |
| 643 | /* write it */ |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 644 | writew_(control, cntlr.control); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 645 | |
| 646 | /* Wait for Cycle Done Status or Flash Cycle Error. */ |
| 647 | status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); |
| 648 | if (status == -1) |
| 649 | return -1; |
| 650 | |
| 651 | if (status & SPIS_FCERR) { |
| 652 | printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n"); |
| 653 | return -1; |
| 654 | } |
| 655 | |
| 656 | if (trans.bytesin) { |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 657 | read_reg(cntlr.data, trans.in, data_length); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 658 | spi_use_in(&trans, data_length); |
| 659 | if (with_address) |
| 660 | trans.offset += data_length; |
| 661 | } |
| 662 | } |
| 663 | |
Werner Zeh | f13a6f9 | 2018-11-14 10:55:52 +0100 | [diff] [blame] | 664 | spi_xfer_exit: |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 665 | /* Clear atomic preop now that xfer is done */ |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 666 | writew_(0, cntlr.preop); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 667 | |
| 668 | return 0; |
| 669 | } |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 670 | |
| 671 | /* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */ |
| 672 | static void ich_hwseq_set_addr(uint32_t addr) |
| 673 | { |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 674 | uint32_t addr_old = readl_(&cntlr.ich9_spi->faddr) & ~0x01FFFFFF; |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 675 | |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 676 | writel_((addr & 0x01FFFFFF) | addr_old, &cntlr.ich9_spi->faddr); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 677 | } |
| 678 | |
| 679 | /* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals. |
| 680 | Resets all error flags in HSFS. |
| 681 | Returns 0 if the cycle completes successfully without errors within |
| 682 | timeout us, 1 on errors. */ |
| 683 | static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, |
| 684 | unsigned int len) |
| 685 | { |
| 686 | uint16_t hsfs; |
| 687 | uint32_t addr; |
| 688 | |
| 689 | timeout /= 8; /* scale timeout duration to counter */ |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 690 | while ((((hsfs = readw_(&cntlr.ich9_spi->hsfs)) & |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 691 | (HSFS_FDONE | HSFS_FCERR)) == 0) && |
| 692 | --timeout) { |
| 693 | udelay(8); |
| 694 | } |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 695 | writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 696 | |
| 697 | if (!timeout) { |
| 698 | uint16_t hsfc; |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 699 | addr = readl_(&cntlr.ich9_spi->faddr) & 0x01FFFFFF; |
| 700 | hsfc = readw_(&cntlr.ich9_spi->hsfc); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 701 | printk(BIOS_ERR, "Transaction timeout between offset 0x%08x and " |
| 702 | "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n", |
| 703 | addr, addr + len - 1, addr, len - 1, |
| 704 | hsfc, hsfs); |
| 705 | return 1; |
| 706 | } |
| 707 | |
| 708 | if (hsfs & HSFS_FCERR) { |
| 709 | uint16_t hsfc; |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 710 | addr = readl_(&cntlr.ich9_spi->faddr) & 0x01FFFFFF; |
| 711 | hsfc = readw_(&cntlr.ich9_spi->hsfc); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 712 | printk(BIOS_ERR, "Transaction error between offset 0x%08x and " |
| 713 | "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n", |
| 714 | addr, addr + len - 1, addr, len - 1, |
| 715 | hsfc, hsfs); |
| 716 | return 1; |
| 717 | } |
| 718 | return 0; |
| 719 | } |
| 720 | |
Furquan Shaikh | c28984d | 2016-11-20 21:04:00 -0800 | [diff] [blame] | 721 | static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset, |
| 722 | size_t len) |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 723 | { |
| 724 | u32 start, end, erase_size; |
| 725 | int ret; |
| 726 | uint16_t hsfc; |
Aaron Durbin | 4ed8e9c | 2019-12-27 14:30:51 -0700 | [diff] [blame] | 727 | unsigned int timeout = 1000 * USECS_PER_MSEC; /* 1 second timeout */ |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 728 | |
| 729 | erase_size = flash->sector_size; |
| 730 | if (offset % erase_size || len % erase_size) { |
| 731 | printk(BIOS_ERR, "SF: Erase offset/length not multiple of erase size\n"); |
| 732 | return -1; |
| 733 | } |
| 734 | |
Furquan Shaikh | 810e2cd | 2016-12-05 20:32:24 -0800 | [diff] [blame] | 735 | ret = spi_claim_bus(&flash->spi); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 736 | if (ret) { |
| 737 | printk(BIOS_ERR, "SF: Unable to claim SPI bus\n"); |
| 738 | return ret; |
| 739 | } |
| 740 | |
| 741 | start = offset; |
| 742 | end = start + len; |
| 743 | |
| 744 | while (offset < end) { |
| 745 | /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 746 | writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 747 | |
| 748 | ich_hwseq_set_addr(offset); |
| 749 | |
| 750 | offset += erase_size; |
| 751 | |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 752 | hsfc = readw_(&cntlr.ich9_spi->hsfc); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 753 | hsfc &= ~HSFC_FCYCLE; /* clear operation */ |
| 754 | hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ |
| 755 | hsfc |= HSFC_FGO; /* start */ |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 756 | writew_(hsfc, &cntlr.ich9_spi->hsfc); |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 757 | if (ich_hwseq_wait_for_cycle_complete(timeout, len)) { |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 758 | printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size); |
| 759 | ret = -1; |
| 760 | goto out; |
| 761 | } |
| 762 | } |
| 763 | |
| 764 | printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n", len, start); |
| 765 | |
| 766 | out: |
Furquan Shaikh | 810e2cd | 2016-12-05 20:32:24 -0800 | [diff] [blame] | 767 | spi_release_bus(&flash->spi); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 768 | return ret; |
| 769 | } |
| 770 | |
| 771 | static void ich_read_data(uint8_t *data, int len) |
| 772 | { |
| 773 | int i; |
| 774 | uint32_t temp32 = 0; |
| 775 | |
| 776 | for (i = 0; i < len; i++) { |
| 777 | if ((i % 4) == 0) |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 778 | temp32 = readl_(cntlr.data + i); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 779 | |
| 780 | data[i] = (temp32 >> ((i % 4) * 8)) & 0xff; |
| 781 | } |
| 782 | } |
| 783 | |
Furquan Shaikh | c28984d | 2016-11-20 21:04:00 -0800 | [diff] [blame] | 784 | static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len, |
| 785 | void *buf) |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 786 | { |
| 787 | uint16_t hsfc; |
| 788 | uint16_t timeout = 100 * 60; |
| 789 | uint8_t block_len; |
| 790 | |
| 791 | if (addr + len > flash->size) { |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 792 | printk(BIOS_ERR, |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 793 | "Attempt to read %x-%x which is out of chip\n", |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 794 | (unsigned int) addr, |
| 795 | (unsigned int) addr+(unsigned int) len); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 796 | return -1; |
| 797 | } |
| 798 | |
| 799 | /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 800 | writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 801 | |
| 802 | while (len > 0) { |
Elyes HAOUAS | 361a935 | 2019-12-18 21:26:33 +0100 | [diff] [blame] | 803 | block_len = MIN(len, cntlr.databytes); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 804 | if (block_len > (~addr & 0xff)) |
| 805 | block_len = (~addr & 0xff) + 1; |
| 806 | ich_hwseq_set_addr(addr); |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 807 | hsfc = readw_(&cntlr.ich9_spi->hsfc); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 808 | hsfc &= ~HSFC_FCYCLE; /* set read operation */ |
| 809 | hsfc &= ~HSFC_FDBC; /* clear byte count */ |
| 810 | /* set byte count */ |
| 811 | hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); |
| 812 | hsfc |= HSFC_FGO; /* start */ |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 813 | writew_(hsfc, &cntlr.ich9_spi->hsfc); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 814 | |
| 815 | if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) |
| 816 | return 1; |
| 817 | ich_read_data(buf, block_len); |
| 818 | addr += block_len; |
| 819 | buf += block_len; |
| 820 | len -= block_len; |
| 821 | } |
| 822 | return 0; |
| 823 | } |
| 824 | |
| 825 | /* Fill len bytes from the data array into the fdata/spid registers. |
| 826 | * |
| 827 | * Note that using len > flash->pgm->spi.max_data_write will trash the registers |
| 828 | * following the data registers. |
| 829 | */ |
| 830 | static void ich_fill_data(const uint8_t *data, int len) |
| 831 | { |
| 832 | uint32_t temp32 = 0; |
| 833 | int i; |
| 834 | |
| 835 | if (len <= 0) |
| 836 | return; |
| 837 | |
| 838 | for (i = 0; i < len; i++) { |
| 839 | if ((i % 4) == 0) |
| 840 | temp32 = 0; |
| 841 | |
| 842 | temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8); |
| 843 | |
| 844 | if ((i % 4) == 3) /* 32 bits are full, write them to regs. */ |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 845 | writel_(temp32, cntlr.data + (i - (i % 4))); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 846 | } |
| 847 | i--; |
| 848 | if ((i % 4) != 3) /* Write remaining data to regs. */ |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 849 | writel_(temp32, cntlr.data + (i - (i % 4))); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 850 | } |
| 851 | |
Furquan Shaikh | c28984d | 2016-11-20 21:04:00 -0800 | [diff] [blame] | 852 | static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len, |
| 853 | const void *buf) |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 854 | { |
| 855 | uint16_t hsfc; |
| 856 | uint16_t timeout = 100 * 60; |
| 857 | uint8_t block_len; |
| 858 | uint32_t start = addr; |
| 859 | |
| 860 | if (addr + len > flash->size) { |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 861 | printk(BIOS_ERR, |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 862 | "Attempt to write 0x%x-0x%x which is out of chip\n", |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 863 | (unsigned int)addr, (unsigned int) (addr+len)); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 864 | return -1; |
| 865 | } |
| 866 | |
| 867 | /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 868 | writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 869 | |
| 870 | while (len > 0) { |
Elyes HAOUAS | 361a935 | 2019-12-18 21:26:33 +0100 | [diff] [blame] | 871 | block_len = MIN(len, cntlr.databytes); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 872 | if (block_len > (~addr & 0xff)) |
| 873 | block_len = (~addr & 0xff) + 1; |
| 874 | |
| 875 | ich_hwseq_set_addr(addr); |
| 876 | |
| 877 | ich_fill_data(buf, block_len); |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 878 | hsfc = readw_(&cntlr.ich9_spi->hsfc); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 879 | hsfc &= ~HSFC_FCYCLE; /* clear operation */ |
| 880 | hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ |
| 881 | hsfc &= ~HSFC_FDBC; /* clear byte count */ |
| 882 | /* set byte count */ |
| 883 | hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); |
| 884 | hsfc |= HSFC_FGO; /* start */ |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 885 | writew_(hsfc, &cntlr.ich9_spi->hsfc); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 886 | |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 887 | if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) { |
| 888 | printk(BIOS_ERR, "SF: write failure at %x\n", |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 889 | addr); |
| 890 | return -1; |
| 891 | } |
| 892 | addr += block_len; |
| 893 | buf += block_len; |
| 894 | len -= block_len; |
| 895 | } |
| 896 | printk(BIOS_DEBUG, "SF: Successfully written %u bytes @ %#x\n", |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 897 | (unsigned int) (addr - start), start); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 898 | return 0; |
| 899 | } |
| 900 | |
Furquan Shaikh | e2fc5e2 | 2017-05-17 17:26:01 -0700 | [diff] [blame] | 901 | static const struct spi_flash_ops spi_flash_ops = { |
| 902 | .read = ich_hwseq_read, |
| 903 | .write = ich_hwseq_write, |
| 904 | .erase = ich_hwseq_erase, |
| 905 | }; |
| 906 | |
Furquan Shaikh | a149157 | 2017-05-17 19:14:06 -0700 | [diff] [blame] | 907 | static int spi_flash_programmer_probe(const struct spi_slave *spi, |
| 908 | struct spi_flash *flash) |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 909 | { |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 910 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 911 | if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) |
Arthur Heymans | c88e370 | 2017-08-20 20:50:17 +0200 | [diff] [blame] | 912 | return spi_flash_generic_probe(spi, flash); |
| 913 | |
Furquan Shaikh | a149157 | 2017-05-17 19:14:06 -0700 | [diff] [blame] | 914 | /* Try generic probing first if spi_is_multichip returns 0. */ |
| 915 | if (!spi_is_multichip() && !spi_flash_generic_probe(spi, flash)) |
| 916 | return 0; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 917 | |
Furquan Shaikh | 810e2cd | 2016-12-05 20:32:24 -0800 | [diff] [blame] | 918 | memcpy(&flash->spi, spi, sizeof(*spi)); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 919 | |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 920 | ich_hwseq_set_addr(0); |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 921 | switch ((cntlr.hsfs >> 3) & 3) { |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 922 | case 0: |
| 923 | flash->sector_size = 256; |
| 924 | break; |
| 925 | case 1: |
| 926 | flash->sector_size = 4096; |
| 927 | break; |
| 928 | case 2: |
| 929 | flash->sector_size = 8192; |
| 930 | break; |
| 931 | case 3: |
| 932 | flash->sector_size = 65536; |
| 933 | break; |
| 934 | } |
| 935 | |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 936 | flash->size = 1 << (19 + (cntlr.flcomp & 7)); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 937 | |
Furquan Shaikh | e2fc5e2 | 2017-05-17 17:26:01 -0700 | [diff] [blame] | 938 | flash->ops = &spi_flash_ops; |
| 939 | |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 940 | if ((cntlr.hsfs & HSFS_FDV) && ((cntlr.flmap0 >> 8) & 3)) |
| 941 | flash->size += 1 << (19 + ((cntlr.flcomp >> 3) & 7)); |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 942 | printk(BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 943 | |
Furquan Shaikh | 30221b4 | 2017-05-15 14:35:15 -0700 | [diff] [blame] | 944 | return 0; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 945 | } |
Furquan Shaikh | a149157 | 2017-05-17 19:14:06 -0700 | [diff] [blame] | 946 | |
Aaron Durbin | 851dde8 | 2018-04-19 21:15:25 -0600 | [diff] [blame] | 947 | static int xfer_vectors(const struct spi_slave *slave, |
| 948 | struct spi_op vectors[], size_t count) |
| 949 | { |
| 950 | return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); |
| 951 | } |
| 952 | |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 953 | #define SPI_FPR_SHIFT 12 |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 954 | #define ICH7_SPI_FPR_MASK 0xfff |
| 955 | #define ICH9_SPI_FPR_MASK 0x1fff |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 956 | #define SPI_FPR_BASE_SHIFT 0 |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 957 | #define ICH7_SPI_FPR_LIMIT_SHIFT 12 |
| 958 | #define ICH9_SPI_FPR_LIMIT_SHIFT 16 |
| 959 | #define ICH9_SPI_FPR_RPE (1 << 15) /* Read Protect */ |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 960 | #define SPI_FPR_WPE (1 << 31) /* Write Protect */ |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 961 | |
| 962 | static u32 spi_fpr(u32 base, u32 limit) |
| 963 | { |
| 964 | u32 ret; |
| 965 | u32 mask, limit_shift; |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 966 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 967 | if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) { |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 968 | mask = ICH7_SPI_FPR_MASK; |
| 969 | limit_shift = ICH7_SPI_FPR_LIMIT_SHIFT; |
| 970 | } else { |
| 971 | mask = ICH9_SPI_FPR_MASK; |
| 972 | limit_shift = ICH9_SPI_FPR_LIMIT_SHIFT; |
| 973 | } |
| 974 | ret = ((limit >> SPI_FPR_SHIFT) & mask) << limit_shift; |
| 975 | ret |= ((base >> SPI_FPR_SHIFT) & mask) << SPI_FPR_BASE_SHIFT; |
| 976 | return ret; |
| 977 | } |
| 978 | |
| 979 | /* |
| 980 | * Protect range of SPI flash defined by [start, start+size-1] using Flash |
| 981 | * Protected Range (FPR) register if available. |
| 982 | * Returns 0 on success, -1 on failure of programming fpr registers. |
| 983 | */ |
| 984 | static int spi_flash_protect(const struct spi_flash *flash, |
Rizwan Qureshi | f9f5093 | 2018-12-31 15:19:16 +0530 | [diff] [blame] | 985 | const struct region *region, |
| 986 | const enum ctrlr_prot_type type) |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 987 | { |
| 988 | u32 start = region_offset(region); |
| 989 | u32 end = start + region_sz(region) - 1; |
| 990 | u32 reg; |
Rizwan Qureshi | f9f5093 | 2018-12-31 15:19:16 +0530 | [diff] [blame] | 991 | u32 protect_mask = 0; |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 992 | int fpr; |
| 993 | uint32_t *fpr_base; |
| 994 | |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 995 | fpr_base = cntlr.fpr; |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 996 | |
| 997 | /* Find first empty FPR */ |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 998 | for (fpr = 0; fpr < cntlr.fpr_max; fpr++) { |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 999 | reg = read32(&fpr_base[fpr]); |
| 1000 | if (reg == 0) |
| 1001 | break; |
| 1002 | } |
| 1003 | |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 1004 | if (fpr == cntlr.fpr_max) { |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 1005 | printk(BIOS_ERR, "ERROR: No SPI FPR free!\n"); |
| 1006 | return -1; |
| 1007 | } |
| 1008 | |
Rizwan Qureshi | f9f5093 | 2018-12-31 15:19:16 +0530 | [diff] [blame] | 1009 | switch (type) { |
| 1010 | case WRITE_PROTECT: |
| 1011 | protect_mask |= SPI_FPR_WPE; |
| 1012 | break; |
| 1013 | case READ_PROTECT: |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 1014 | if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) |
Rizwan Qureshi | f9f5093 | 2018-12-31 15:19:16 +0530 | [diff] [blame] | 1015 | return -1; |
| 1016 | protect_mask |= ICH9_SPI_FPR_RPE; |
| 1017 | break; |
| 1018 | case READ_WRITE_PROTECT: |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 1019 | if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) |
Rizwan Qureshi | f9f5093 | 2018-12-31 15:19:16 +0530 | [diff] [blame] | 1020 | return -1; |
| 1021 | protect_mask |= (ICH9_SPI_FPR_RPE | SPI_FPR_WPE); |
| 1022 | break; |
| 1023 | default: |
| 1024 | printk(BIOS_ERR, "ERROR: Seeking invalid protection!\n"); |
| 1025 | return -1; |
| 1026 | } |
| 1027 | |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 1028 | /* Set protected range base and limit */ |
Rizwan Qureshi | f9f5093 | 2018-12-31 15:19:16 +0530 | [diff] [blame] | 1029 | reg = spi_fpr(start, end) | protect_mask; |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 1030 | |
| 1031 | /* Set the FPR register and verify it is protected */ |
| 1032 | write32(&fpr_base[fpr], reg); |
Arthur Heymans | f957201 | 2019-06-11 11:15:10 +0200 | [diff] [blame] | 1033 | if (reg != read32(&fpr_base[fpr])) { |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 1034 | printk(BIOS_ERR, "ERROR: Unable to set SPI FPR %d\n", fpr); |
| 1035 | return -1; |
| 1036 | } |
| 1037 | |
| 1038 | printk(BIOS_INFO, "%s: FPR %d is enabled for range 0x%08x-0x%08x\n", |
| 1039 | __func__, fpr, start, end); |
| 1040 | return 0; |
| 1041 | } |
| 1042 | |
Arthur Heymans | 92185e3 | 2019-05-28 13:06:34 +0200 | [diff] [blame] | 1043 | void spi_finalize_ops(void) |
| 1044 | { |
Arthur Heymans | 92185e3 | 2019-05-28 13:06:34 +0200 | [diff] [blame] | 1045 | u16 spi_opprefix; |
| 1046 | u16 optype = 0; |
Arthur Heymans | 50b4f78 | 2019-09-23 11:49:17 +0200 | [diff] [blame] | 1047 | struct intel_swseq_spi_config spi_config_default = { |
Arthur Heymans | 92185e3 | 2019-05-28 13:06:34 +0200 | [diff] [blame] | 1048 | {0x06, 0x50}, /* OPPREFIXES: EWSR and WREN */ |
Arthur Heymans | 50b4f78 | 2019-09-23 11:49:17 +0200 | [diff] [blame] | 1049 | { /* OPCODE and OPTYPE */ |
Arthur Heymans | 92185e3 | 2019-05-28 13:06:34 +0200 | [diff] [blame] | 1050 | {0x01, WRITE_NO_ADDR}, /* WRSR: Write Status Register */ |
| 1051 | {0x02, WRITE_WITH_ADDR}, /* BYPR: Byte Program */ |
| 1052 | {0x03, READ_WITH_ADDR}, /* READ: Read Data */ |
| 1053 | {0x05, READ_NO_ADDR}, /* RDSR: Read Status Register */ |
| 1054 | {0x20, WRITE_WITH_ADDR}, /* SE20: Sector Erase 0x20 */ |
| 1055 | {0x9f, READ_NO_ADDR}, /* RDID: Read ID */ |
| 1056 | {0xd8, WRITE_WITH_ADDR}, /* BED8: Block Erase 0xd8 */ |
| 1057 | {0x0b, READ_WITH_ADDR}, /* FAST: Fast Read */ |
| 1058 | } |
| 1059 | }; |
Arthur Heymans | 50b4f78 | 2019-09-23 11:49:17 +0200 | [diff] [blame] | 1060 | struct intel_swseq_spi_config spi_config_aai_write = { |
| 1061 | {0x06, 0x50}, /* OPPREFIXES: EWSR and WREN */ |
| 1062 | { /* OPCODE and OPTYPE */ |
| 1063 | {0x01, WRITE_NO_ADDR}, /* WRSR: Write Status Register */ |
| 1064 | {0x02, WRITE_WITH_ADDR}, /* BYPR: Byte Program */ |
| 1065 | {0x03, READ_WITH_ADDR}, /* READ: Read Data */ |
| 1066 | {0x05, READ_NO_ADDR}, /* RDSR: Read Status Register */ |
| 1067 | {0x20, WRITE_WITH_ADDR}, /* SE20: Sector Erase 0x20 */ |
| 1068 | {0x9f, READ_NO_ADDR}, /* RDID: Read ID */ |
| 1069 | {0xad, WRITE_NO_ADDR}, /* Auto Address Increment Word Program */ |
| 1070 | {0x04, WRITE_NO_ADDR} /* Write Disable */ |
| 1071 | } |
| 1072 | }; |
| 1073 | const struct spi_flash *flash = boot_device_spi_flash(); |
| 1074 | struct intel_swseq_spi_config *spi_config = &spi_config_default; |
Arthur Heymans | 92185e3 | 2019-05-28 13:06:34 +0200 | [diff] [blame] | 1075 | int i; |
| 1076 | |
Arthur Heymans | 50b4f78 | 2019-09-23 11:49:17 +0200 | [diff] [blame] | 1077 | /* |
| 1078 | * Some older SST SPI flashes support AAI write but use 0xaf opcde for |
| 1079 | * that. Flashrom uses the byte program opcode to write those flashes, |
| 1080 | * so this configuration is fine too. SST25VF064C (id = 0x4b) is an |
| 1081 | * exception. |
| 1082 | */ |
| 1083 | if (flash && flash->vendor == VENDOR_ID_SST && (flash->model & 0x00ff) != 0x4b) |
| 1084 | spi_config = &spi_config_aai_write; |
| 1085 | |
Arthur Heymans | 92185e3 | 2019-05-28 13:06:34 +0200 | [diff] [blame] | 1086 | if (spi_locked()) |
| 1087 | return; |
| 1088 | |
Arthur Heymans | 50b4f78 | 2019-09-23 11:49:17 +0200 | [diff] [blame] | 1089 | intel_southbridge_override_spi(spi_config); |
Arthur Heymans | 92185e3 | 2019-05-28 13:06:34 +0200 | [diff] [blame] | 1090 | |
Arthur Heymans | 50b4f78 | 2019-09-23 11:49:17 +0200 | [diff] [blame] | 1091 | spi_opprefix = spi_config->opprefixes[0] |
| 1092 | | (spi_config->opprefixes[1] << 8); |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 1093 | writew_(spi_opprefix, cntlr.preop); |
Arthur Heymans | 50b4f78 | 2019-09-23 11:49:17 +0200 | [diff] [blame] | 1094 | for (i = 0; i < ARRAY_SIZE(spi_config->ops); i++) { |
| 1095 | optype |= (spi_config->ops[i].type & 3) << (i * 2); |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 1096 | writeb_(spi_config->ops[i].op, &cntlr.opmenu[i]); |
Arthur Heymans | 92185e3 | 2019-05-28 13:06:34 +0200 | [diff] [blame] | 1097 | } |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 1098 | writew_(optype, cntlr.optype); |
Arthur Heymans | 92185e3 | 2019-05-28 13:06:34 +0200 | [diff] [blame] | 1099 | } |
| 1100 | |
| 1101 | __weak void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config) |
| 1102 | { |
| 1103 | } |
| 1104 | |
Furquan Shaikh | a149157 | 2017-05-17 19:14:06 -0700 | [diff] [blame] | 1105 | static const struct spi_ctrlr spi_ctrlr = { |
Aaron Durbin | 851dde8 | 2018-04-19 21:15:25 -0600 | [diff] [blame] | 1106 | .xfer_vector = xfer_vectors, |
Arthur Heymans | a9c1a5f | 2019-06-15 18:21:58 +0200 | [diff] [blame] | 1107 | .max_xfer_size = member_size(struct ich9_spi_regs, fdata), |
Furquan Shaikh | a149157 | 2017-05-17 19:14:06 -0700 | [diff] [blame] | 1108 | .flash_probe = spi_flash_programmer_probe, |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 1109 | .flash_protect = spi_flash_protect, |
Furquan Shaikh | a149157 | 2017-05-17 19:14:06 -0700 | [diff] [blame] | 1110 | }; |
| 1111 | |
Furquan Shaikh | 2cd03f1 | 2017-05-18 14:58:32 -0700 | [diff] [blame] | 1112 | const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { |
| 1113 | { |
| 1114 | .ctrlr = &spi_ctrlr, |
| 1115 | .bus_start = 0, |
| 1116 | .bus_end = 0, |
| 1117 | }, |
| 1118 | }; |
| 1119 | |
| 1120 | const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); |